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stm8s005k6 stm8s005c6 v alue line, 16 mhz stm8s 8-bit mcu, 32 kbytes flash, data eeprom,10-bit adc, timers, uar t , spi, i2c features core ? 16 mhz advanced stm8 core with harvard architecture and 3-stage pipeline ? extended instruction set memories ? medium-density flash/eeprom: - program memory: 32 kbytes of flash memory; data retention 20 years at 55c after 100 cycles - data memory: 128 bytes of true data eeprom; endurance up to 100 k write/erase cycles ? ram: 2 kbytes clock, reset and supply management ? 2.95 v to 5.5 v operating voltage ? flexible clock control, 4 master clock sources: - low power crystal resonator oscillator - external clock input - internal, user-trimmable 16 mhz rc - internal low power 128 khz rc ? clock security system with clock monitor ? power management: - low power modes (wait, active-halt, halt) - switch-of f peripheral clocks individually ? permanently active, low consumption power-on and power-down reset interrupt management ? nested interrupt controller with 32 interrupts ? up to 37 external interrupts on 6 vectors t imers ? 2x 16-bit general purpose timers, with 2+3 capcom channels (ic, oc or pwm) ? advanced control timer: 16-bit, 4 capcom channels, 3 complementary outputs, dead-time insertion and flexible synchronization ? 8-bit basic timer with 8-bit prescaler ? auto wake-up timer ? window and independent watchdog timers communications interfaces ? uar t with clock output for synchronous operation, smartcard, irda, lin ? spi interface up to 8 mbit/s ? i 2 c interface up to 400 kbit/s analog-to-digital converter (adc) ? 10-bit, 1 lsb adc with up to 10 multiplexed channels, scan mode and analog watchdog i/os ? up to 38 i/os on a 48-pin package including 16 high sink outputs ? highly robust i/o design, immune against current injection development support ? embedded single wire interface module (swim) for fast on-chip programming and non intrusive debugging 1 / 103 docid022186 rev 3 june 2012 www .st.com lqfp48 7x7 lqfp32 7x7
contents 1 introduction .............................................................................................................. 7 2 description ............................................................................................................... 8 3 block diagram .......................................................................................................... 9 4 product overview ................................................................................................... 10 4.1 central processing unit stm8 ..................................................................................... 10 4.2 single wire interface module (swim) and debug module (dm) .................................. 10 4.3 interrupt controller ....................................................................................................... 11 4.4 flash program and data eeprom memory ................................................................ 11 4.5 clock controller ............................................................................................................ 12 4.6 power management .................................................................................................... 13 4.7 w atchdog timers .......................................................................................................... 14 4.8 auto wakeup counter ................................................................................................... 14 4.9 beeper ........................................................................................................................ 14 4.10 tim1 - 16-bit advanced control timer ......................................................................... 15 4.1 1 tim2, tim3 - 16-bit general purpose timers .............................................................. 15 4.12 tim4 - 8-bit basic timer .............................................................................................. 15 4.13 analog-to-digital converter (adc1) ............................................................................ 16 4.14 communication interfaces ......................................................................................... 16 4.14.1 uar t2 ............................................................................................... 16 4.14.2 spi ..................................................................................................... 17 4.14.3 i2c ...................................................................................................... 18 5 pinout and pin description ................................................................................... 19 5.1 stm8s005 pinouts and pin description ....................................................................... 20 5.1.1 alternate function remapping ............................................................... 24 6 memory and register map ..................................................................................... 25 6.1 memory map ................................................................................................................ 25 6.2 register map ............................................................................................................... 26 6.2.1 i/o port hardware register map ............................................................ 26 6.2.2 general hardware register map ........................................................... 29 6.2.3 cpu/swim/debug module/interrupt controller registers ...................... 39 7 interrupt vector mapping ...................................................................................... 42 8 option bytes ........................................................................................................... 44 9 electrical characteristics ...................................................................................... 49 9.1 parameter conditions ................................................................................................... 49 9.1.1 minimum and maximum values ........................................................... 49 9.1.2 t ypical values ....................................................................................... 49 9.1.3 t ypical curves ...................................................................................... 49 docid022186 rev 3 2 / 103 stm8s005k6 stm8s005c6 contents
9.1.4 t ypical current consumption ................................................................ 49 9.1.5 loading capacitor ................................................................................. 50 9.1.6 pin input voltage ................................................................................... 50 9.2 absolute maximum ratings .......................................................................................... 50 9.3 operating conditions ................................................................................................... 52 9.3.1 vcap external capacitor ...................................................................... 54 9.3.2 supply current characteristics .............................................................. 55 9.3.3 external clock sources and timing characteristics ............................... 66 9.3.4 internal clock sources and timing characteristics ................................. 68 9.3.5 memory characteristics ........................................................................ 70 9.3.6 i/o port pin characteristics ................................................................... 72 9.3.7 t ypical output level curves ................................................................... 75 9.3.8 reset pin characteristics ...................................................................... 79 9.3.9 spi serial peripheral interface .............................................................. 81 9.3.10 i 2 c interface characteristics ............................................................... 84 9.3.1 1 10-bit adc characteristics .................................................................. 86 9.3.12 emc characteristics ........................................................................... 89 10 package information ........................................................................................... 93 10.1 48-pin lqfp package mechanical data .................................................................... 93 10.2 32-pin lqfp package mechanical data .................................................................... 95 1 1 thermal characteristics ....................................................................................... 97 1 1.1 reference document ................................................................................................. 97 1 1.2 selecting the product temperature range .................................................................. 97 12 ordering information ........................................................................................... 99 13 stm8 development tools .................................................................................. 100 13.1 emulation and in-circuit debugging tools ................................................................. 100 13.2 software tools .......................................................................................................... 100 13.2.1 stm8 toolset .................................................................................... 101 13.2.2 c and assembly toolchains .............................................................. 101 13.3 programming tools .................................................................................................. 101 14 revision history ................................................................................................. 102 3 / 103 docid022186 rev 3 contents stm8s005k6 stm8s005c6
list of tables t able 1. stm8s005xx value line features ................................................................................................ 8 t able 2. peripheral clock gating bit assignments in clk_pckenr1/2 registers .................................. 13 t able 3. tim timer features ................................................................................................................... 15 t able 4. legend/abbreviations for pinout tables ................................................................................... 19 t able 5. pin description for stm8s005 microcontrollers ....................................................................... 21 t able 6. flash, data eeprom and ram boundary addresses ............................................................ 26 t able 7. i/o port hardware register map ................................................................................................ 26 t able 8. general hardware register map ................................................................................................ 29 t able 9. cpu/swim/debug module/interrupt controller registers .......................................................... 39 t able 10. interrupt mapping ................................................................................................................... 42 t able 1 1. option bytes ........................................................................................................................... 44 t able 12. option byte description ........................................................................................................... 45 t able 13. description of alternate function remapping bits [7:0] of opt2 .............................................. 47 t able 14. v oltage characteristics ........................................................................................................... 50 t able 15. current characteristics ........................................................................................................... 51 t able 16. thermal characteristics .......................................................................................................... 52 t able 17. general operating conditions ................................................................................................. 53 t able 18. operating conditions at power-up/power-down ...................................................................... 54 t able 19. t otal current consumption with code execution in run mode at v dd = 5 v ............................. 55 t able 20. t otal current consumption with code execution in run mode at v dd = 3.3 v .......................... 66 t able 21. t otal current consumption in wait mode at v dd = 5 v ............................................................ 58 t able 22. t otal current consumption in wait mode at v dd = 3.3 v ......................................................... 58 t able 23. t otal current consumption in active halt mode at v dd = 5 v .................................................. 59 t able 24. t otal current consumption in active halt mode at v dd = 3.3 v ............................................... 60 t able 25. t otal current consumption in halt mode at v dd = 5 v ............................................................. 61 t able 26. t otal current consumption in halt mode at v dd = 3.3 v .......................................................... 61 t able 27. w akeup times ......................................................................................................................... 61 t able 28. t otal current consumption and timing in forced reset state .................................................... 92 t able 29. peripheral current consumption ............................................................................................. 63 t able 30. hse user external clock characteristics ................................................................................. 66 t able 31. hse oscillator characteristics ................................................................................................. 67 t able 32. hsi oscillator characteristics .................................................................................................. 68 t able 33. lsi oscillator characteristics ................................................................................................... 70 t able 34. ram and hardware registers .................................................................................................. 70 t able 35. flash program memory/data eeprom memory .................................................................... 71 t able 36. i/o static characteristics ......................................................................................................... 72 t able 37. output driving current (standard ports) .................................................................................. 74 t able 38. output driving current (true open drain ports) ........................................................................ 74 t able 39. output driving current (high sink ports) .................................................................................. 74 t able 40. nrst pin characteristics ........................................................................................................ 79 t able 41. spi characteristics .................................................................................................................. 81 t able 42. i 2 c characteristics .................................................................................................................. 84 t able 43. adc characteristics ................................................................................................................ 86 t able 44. adc accuracy with r ain < 10 k , v dda = 5 v ....................................................................... 87 t able 45. adc accuracy with r ain < 10 k r ain , v dda = 3.3 v ............................................................ 88 t able 46. ems data ................................................................................................................................ 90 t able 47. emi data ................................................................................................................................. 91 docid022186 rev 3 4 / 103 stm8s005k6 stm8s005c6 list of tables
t able 48. esd absolute maximum ratings ............................................................................................. 92 t able 49. electrical sensitivities ............................................................................................................. 92 t able 50. 48-pin low profile quad flat package mechanical data ............................................................ 93 t able 51. 32-pin low profile quad flat package mechanical data ......................................................... 102 t able 52. thermal characteristics (1) ...................................................................................................... 97 t able 53. document revision history ................................................................................................... 102 5 / 103 docid022186 rev 3 list of tables stm8s005k6 stm8s005c6
list of figures figure 1. stm8s005xx value line block diagram ..................................................................................... 9 figure 2. flash memory organization .................................................................................................... 12 figure 3. lqfp 48-pin pinout ................................................................................................................. 20 figure 4. lqfp 32-pin pinout ................................................................................................................ 21 figure 5. memory map ........................................................................................................................... 25 figure 6. supply current measurement conditions ................................................................................ 49 figure 7. pin loading conditions ............................................................................................................. 50 figure 8. pin input voltage ..................................................................................................................... 50 figure 9. f cpumax versus v dd ................................................................................................................ 54 figure 10. external capacitor c ext ....................................................................................................... 55 figure 1 1. t yp. i dd(run) vs. v dd , hse user external clock, f cpu = 16 mhz ........................................... 64 figure 12. t yp. i dd(run) vs. f cpu , hse user external clock, v dd = 5 v .................................................. 64 figure 13. t yp. i dd(run) vs. v dd , hsi rc osc, f cpu = 16 mhz .............................................................. 65 figure 14. t yp. i dd(wfi) vs. v dd , hse user external clock, f cpu = 16 mhz ............................................ 65 figure 15. t yp. i dd(wfi) vs. f cpu , hse user external clock v dd = 5 v .................................................... 65 figure 16. t yp. i dd(wfi) vs. v dd , hsi rc osc, f cpu = 16 mhz ................................................................ 66 figure 17. hse external clocksource ..................................................................................................... 67 figure 18. hse oscillator circuit diagram ............................................................................................... 68 figure 19. t ypical hsi frequency variation vs v dd @ 3 temperatures .................................................. 69 figure 20. t ypical lsi frequency variation vs v dd @ 3 temperatures ................................................... 70 figure 21. t ypical v il and v ih vs v dd @ 3 temperatures ...................................................................... 73 figure 22. t ypical pull-up resistance vs v dd @ 3 temperatures ............................................................ 73 figure 23. t ypical pull-up current vs v dd @ 3 temperatures ................................................................. 73 figure 24. t yp. v ol @ v dd = 5 v (standard ports) ................................................................................ 75 figure 25. t yp. v ol @ v dd = 3.3 v (standard ports) ............................................................................. 76 figure 26. t yp. v ol @ v dd = 5 v (true open drain ports) ...................................................................... 76 figure 27. t yp. v ol @ v dd = 3.3 v (true open drain ports) ................................................................... 76 figure 28. t yp. v ol @ v dd = 5 v (high sink ports) ................................................................................ 77 figure 29. t yp. v ol @ v dd = 3.3 v (high sink ports) ............................................................................. 77 figure 30. t yp. v dd - v oh @ v dd = 5 v (standard ports) ....................................................................... 77 figure 31. t yp. v dd - v oh @ v dd = 3.3 v (standard ports) .................................................................... 78 figure 32. t yp. v dd - v oh @ v dd = 5 v (high sink ports) ...................................................................... 78 figure 33. t yp. v dd - v oh @ v dd = 3.3 v (high sink ports) ................................................................... 78 figure 34. t ypical nrst v il and v ih vs v dd @ 3 temperatures ........................................................... 80 figure 35. t ypical nrst pull-up resistance vs v dd @ 3 temperatures ................................................. 80 figure 36. t ypical nrst pull-up current vs v dd @ 3 temperatures ...................................................... 80 figure 37. recommended reset pin protection ...................................................................................... 81 figure 38. spi timing diagram - slave mode and cpha = 0 .................................................................. 83 figure 39. spi timing diagram - slave mode and cpha = 1 (1) ............................................................. 83 figure 40. spi timing diagram - master mode (1) ................................................................................... 84 figure 41. t ypical application with i 2 c bus and timing diagram (1) ....................................................... 85 figure 42. adc accuracy characteristics ............................................................................................... 89 figure 43. t ypical application with adc ................................................................................................ 89 figure 44. 48-pin low profile quad flat package (7 x 7) .......................................................................... 93 figure 45. 32-pin low profile quad flat package (7 x 7) .......................................................................... 95 figure 46. stm8s005xx value line ordering information scheme ......................................................... 99 docid022186 rev 3 6 / 103 stm8s005k6 stm8s005c6 list of figures
introduction 1 this datasheet contains the description of the device features, pinout, electrical characteristics, mechanical data and ordering information. ? for complete information on the stm8s microcontroller memory , registers and peripherals, please refer to the stm8s microcontroller family reference manual (rm0016). ? for information on programming, erasing and protection of the internal flash memory please refer to the stm8s flash programming manual (pm0051). ? for information on the debug and swim (single wire interface module) refer to the stm8 swim communication protocol and debug module user manual (um0470). ? for information on the stm8 core, please refer to the stm8 cpu programming manual (pm0044). 7 / 103 docid022186 rev 3 introduction stm8s005k6 stm8s005c6
description 2 the stm8s005xx value line 8-bit microcontrollers of fer 32 kbytes of flash program memory , plus 128 bytes of data eeprom. they are referred to as medium-density devices in the stm8s microcontroller family reference manual (rm0016). all devices of the stm8s005xx value line provide the following benefits: performance, robustness, reduced system cost, and short develoment cycles. device performance and robustness are ensured by true data eeprom supporting up to 100 000 write/erase cycles, advanced core and peripherals made in a state-of-the art technology , a 16 mhz clock frequency , robust i/os, independent watchdogs with separate clock source, and a clock security system. the system cost is reduced thanks to high system integration level with internal clock oscillators, watchdog and brown-out reset. common family product architecture with compatible pinout, memory map and modular peripherals allow application scalability and reduced development cycles. all products operate from a 2.95 to 5.5 v supply voltage. full documentation is of fered as well as a wide choice of development tools. t able 1: stm8s005xx value line features stm8s005k6 stm8s005c6 device 32 48 pin count 25 38 maximum number of gpios 23 35 ext. interrupt pins 8 9 t imer capcom channels 3 3 t imer complementary outputs 7 10 a/d converter channels 12 16 high sink i/os 32k 32k medium density flash program memory (bytes) 128 128 data eeprom (bytes) 2k 2k ram (bytes) advanced control timer (tim1), general-purpose timers (tim2 and tim3), basic timer (tim4) spi, i 2 c, uar t , window wdg, independent wdg, adc peripheral set docid022186 rev 3 8 / 103 stm8s005k6 stm8s005c6 description
block diagram 3 figure 1: stm8s005xx value line block diagram 9 / 103 docid022186 rev 3 block diagram stm8s005k6 stm8s005c6 xt al 1-16 mhz rc int. 16 mhz rc int. 128 khz stm8 core deb ug/swim i 2 c spi u ar t2 16-bit gener al pur pose a wu timer reset b loc k reset por/ pdr bor cloc k controller detector cloc k to per ipher als and core 8 mbit/s up to 10 channels address and data b us windo w wdg independent wdg 32 kb ytes 128 b ytes 2 kb ytes boot r om adc1 reset 400 kbit/s single wire deb ug interf . prog r am flash 16-bit adv anced control timer (tim1) timers (tim2, tim3) 8-bit basic timer (tim4) data eepr om ram master/sla v e autosynchro lin master spi em ul. beeper 1/2/4 khz beep 5 capcom channels up to 4 capcom channels +3 up to complementar y outputs
product overview 4 the following section intends to give an overview of the basic features of the device functional modules and peripherals. for more detailed information please refer to the corresponding family reference manual (rm0016). central processing unit stm8 4.1 the 8-bit stm8 core is designed for code ef ficiency and performance. it contains 6 internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect and relative addressing and 80 instructions. architecture and registers ? harvard architecture ? 3-stage pipeline ? 32-bit wide program memory bus - single cycle fetching for most instructions ? x and y 16-bit index registers - enabling indexed addressing modes with or without of fset and read-modify-write type data manipulations ? 8-bit accumulator ? 24-bit program counter - 16-mbyte linear memory space ? 16-bit stack pointer - access to a 64 k-level stack ? 8-bit condition code register - 7 condition flags for the result of the last instruction addressing ? 20 addressing modes ? indexed indirect addressing mode for look-up tables located anywhere in the address space ? stack pointer relative addressing mode for local variables and parameter passing instruction set ? 80 instructions with 2-byte average instruction size ? standard data movement and logic/arithmetic functions ? 8-bit by 8-bit multiplication ? 16-bit by 8-bit and 16-bit by 16-bit division ? bit manipulation ? data transfer between stack and accumulator (push/pop) with direct stack access ? data transfer using the x and y registers or direct memory-to-memory transfers single wire interface module (swim) and debug module (dm) 4.2 the single wire interface module and debug module permits non-intrusive, real-time in-circuit debugging and fast memory programming. docid022186 rev 3 10 / 103 stm8s005k6 stm8s005c6 product overview
swim single wire interface module for direct access to the debug module and memory programming. the interface can be activated in all device operation modes. the maximum data transmission speed is 145 bytes/ms. debug module the non-intrusive debugging module features a performance close to a full-featured emulator . beside memory and peripherals, also cpu operation can be monitored in real-time by means of shadow registers. ? r/w to ram and peripheral registers in real-time ? r/w access to all resources by stalling the cpu ? breakpoints on all program-memory instructions (software breakpoints) ? t wo advanced breakpoints, 23 predefined configurations interrupt controller 4.3 ? nested interrupts with three software priority levels ? 32 interrupt vectors with hardware priority ? up to 37 external interrupts on 6 vectors including tli ? t rap and reset interrupts flash program and data eeprom memory 4.4 ? 32 kbytes of flash program single voltage flash memory ? 128 bytes true data eeprom ? read while write: w riting in data memory possible while executing code in program memory ? user option byte area w rite protection (wp) w rite protection of flash program memory and data eeprom is provided to avoid unintentional overwriting of memory that could result from a user software malfunction. there are two levels of write protection. the first level is known as mass (memory access security system). mass is always enabled and protects the main flash program memory , data eeprom and option bytes. t o perform in-application programming (iap), this write protection can be removed by writing a mass key sequence in a control register . this allows the application to write to data eeprom, modify the contents of main program memory or the device option bytes. a second level of write protection, can be enabled to further protect a specific area of memory known as ubc (user boot code). refer to the figure below . the size of the ubc is programmable through the ubc option byte, in increments of 1 page (512 bytes) by programming the ubc option byte in icp mode. this divides the program memory into two areas: ? main program memory: 32 kbytes minus ubc ? user-specific boot code (ubc): configurable up to 32 kbytes 1 1 / 103 docid022186 rev 3 product overview stm8s005k6 stm8s005c6
the ubc area remains write-protected during in-application programming. this means that the mass keys do not unlock the ubc area. it protects the memory used to store the boot program, specific code libraries, reset and interrupt vectors, the reset routine and usually the iap and communication routines. figure 2: flash memory organization read-out protection (rop) the read-out protection blocks reading and writing the flash program memory and data eeprom memory in icp mode (and debug mode). once the read-out protection is activated, any attempt to toggle its status triggers a global erase of the program and data memory . even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller . clock controller 4.5 the clock controller distributes the system clock (f master ) coming from dif ferent oscillators to the core and the peripherals. it also manages clock gating for low power modes and ensures clock robustness. features ? clock prescaler: t o get the best compromise between speed and current consumption the clock frequency to the cpu and peripherals can be adjusted by a programmable prescaler . ? safe clock switching: clock sources can be changed safely on the fly in run mode through a configuration register . the clock signal is not switched until the new clock source is ready . the design guarantees glitch-free switching. ? clock management: t o reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory . ? master clock sources: four dif ferent clock sources can be used to drive the master clock: - 1-16 mhz high-speed external crystal (hse) - up to 16 mhz high-speed user-external clock (hse user-ext) docid022186 rev 3 12 / 103 stm8s005k6 stm8s005c6 product overview prog r ammab le area data prog r am memor y area data memor y area ( 128 b ytes) eepr om ubc area remains wr ite protected dur ing iap memor y wr ite access possib le f or iap (1 page steps) option b ytes (2 first pages) up to medium density flash prog r am memor y ? (32 kb ytes) from 1 kb yte 32 kb ytes
- 16 mhz high-speed internal rc oscillator (hsi) - 128 khz low-speed internal rc (lsi) ? startup clock: after reset, the microcontroller restarts by default with an internal 2 mhz clock (hsi/8). the prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. ? clock security system (css): this feature can be enabled by software. if an hse clock failure occurs, the internal rc (16 mhz/8) is automatically selected by the css and an interrupt can optionally be generated. ? configurable main clock output (cco): this outputs an external clock for use by the application. t able 2: peripheral clock gating bit assignments in clk_pckenr1/2 registers peripheral clock bit peripheral clock bit peripheral clock bit peripheral clock bit adc pcken2 3 reserved pcken2 7 uar t2 pcken1 3 tim1 pcken1 7 a wu pcken2 2 reserved pcken2 6 reserved pcken1 2 tim3 pcken1 6 reserved pcken2 1 reserved pcken2 5 spi pcken1 1 tim2 pcken1 5 reserved pcken2 0 reserved pcken2 4 i 2 c pcken1 0 tim4 pcken1 4 power management 4.6 for ef ficent power management, the application can be put in one of four dif ferent low-power modes. y ou can configure each mode to obtain the best compromise between lowest power consumption, fastest start-up time and available wakeup sources. ? w ait mode: in this mode, the cpu is stopped, but peripherals are kept running. the wakeup is performed by an internal or external interrupt or reset. ? active halt mode with regulator on: in this mode, the cpu and peripheral clocks are stopped. an internal wakeup is generated at programmable intervals by the auto wake up unit (a wu). the main voltage regulator is kept powered on, so current consumption is higher than in active halt mode with regulator of f, but the wakeup time is faster . w akeup is triggered by the internal a wu interrupt, external interrupt or reset. ? active halt mode with regulator of f: this mode is the same as active halt with regulator on, except that the main voltage regulator is powered of f, so the wake up time is slower . ? halt mode: in this mode the microcontroller uses the least power . the cpu and peripheral clocks are stopped, the main voltage regulator is powered of f. w akeup is triggered by external event or reset. 13 / 103 docid022186 rev 3 product overview stm8s005k6 stm8s005c6
w atchdog timers 4.7 the watchdog system is based on two independent timers providing maximum security to the applications. activation of the watchdog timers is controlled by option bytes or by software. once activated, the watchdogs cannot be disabled by the user program without performing a reset. w indow watchdog timer the window watchdog is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence. the window function can be used to trim the watchdog behavior to match the application perfectly . the application software must refresh the counter before time-out and during a limited time window . a reset is generated in two situations: 1. t imeout: at 16 mhz cpu clock the time-out period can be adjusted between 75 s up to 64 ms. 2. refresh out of window: the downcounter is refreshed before its value is lower than the one stored in the window register . independent watchdog timer the independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures. it is clocked by the 128 khz lsi internal rc clock source, and thus stays active even in case of a cpu clock failure the iwdg time base spans from 60 s to 1 s. auto wakeup counter 4.8 ? used for auto wakeup from active halt mode ? clock source: internal 128 khz internal low frequency rc oscillator or external clock ? lsi clock can be internally connected to tim3 input capture channel 1 for calibration beeper 4.9 the beeper function outputs a signal on the beep pin for sound generation. the signal is in the range of 1, 2 or 4 khz. the beeper output port is only available through the alternate function remap option bit afr7. docid022186 rev 3 14 / 103 stm8s005k6 stm8s005c6 product overview
tim1 - 16-bit advanced control timer 4.10 this is a high-end timer designed for a wide range of control applications. with its complementary outputs, dead-time control and center-aligned pwm capability , the field of applications is extended to motor control, lighting and half-bridge driver ? 16-bit up, down and up/down autoreload counter with 16-bit prescaler ? four independent capture/compare channels (capcom) configurable as input capture, output compare, pwm generation (edge and center aligned mode) and single pulse mode output ? synchronization module to control the timer with external signals ? break input to force the timer outputs into a defined state ? three complementary outputs with adjustable dead time ? encoder mode ? interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break tim2, tim3 - 16-bit general purpose timers 4.1 1 ? 16-bit autoreload (ar) up-counter ? 15-bit prescaler adjustable to fixed power of 2 ratios 132768 ? t imers with 3 or 2 individually configurable capture/compare channels ? pwm mode ? interrupt sources: 2 or 3 x input capture/output compare, 1 x overflow/update tim4 - 8-bit basic timer 4.12 ? 8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128 ? clock source: cpu clock ? interrupt source: 1 x overflow/update t able 3: tim timer features t imer synchronization/ chaining ext. trigger complem. outputs capcom channels counting mode prescaler counter size (bits) t imer no y es 3 4 up/ down any integer from 1 to 65536 16 tim1 no 0 3 up any power of 2 from 1 to 32768 16 tim2 no 0 2 up any power of 2 from 1 to 32768 16 tim3 15 / 103 docid022186 rev 3 product overview stm8s005k6 stm8s005c6
t imer synchronization/ chaining ext. trigger complem. outputs capcom channels counting mode prescaler counter size (bits) t imer no 0 0 up any power of 2 from 1 to 128 8 tim4 analog-to-digital converter (adc1) 4.13 the stm8s105xx products contain a 10-bit successive approximation a/d converter (adc1) with up to 10 multiplexed input channels and the following main features: ? input voltage range: 0 to v dda ? conversion time: 14 clock cycles ? single and continuous and buf fered continuous conversion modes ? buf fer size (n x 10 bits) where n = number of input channels ? scan mode for single and continuous conversion of a sequence of channels ? analog watchdog capability with programmable upper and lower thresholds ? analog watchdog interrupt ? external trigger input ? t rigger from tim1 trgo ? end of conversion (eoc) interrupt note : additional ain12 analog input is not selectable in adc scan mode or with analog watchdog. v alues converted from ain12 are stored only into the adc_drh/adc_drl registers. communication interfaces 4.14 the following communication interfaces are implemented: ? uar t2: full feature uar t , synchronous mode, spi master mode, smartcard mode, irda mode, lin2.1 master/slave capability ? spi : full and half-duplex, 8 mbit/s ? i2c: up to 400 kbit/s uart2 4.14.1 main features ? one mbit/s full duplex sci ? spi emulation ? high precision baud rate generator ? smartcard emulation ? irda sir encoder decoder docid022186 rev 3 16 / 103 stm8s005k6 stm8s005c6 product overview
? lin master mode ? lin slave mode asynchronous communication (uart mode) ? full duplex communication - nrz standard format (mark/space) ? programmable transmit and receive baud rates up to 1 mbit/s (f cpu /16) and capable of following any standard baud rate regardless of the input frequency ? separate enable bits for transmitter and receiver ? t wo receiver wakeup modes: - address bit (msb) - idle line (interrupt) ? t ransmission error detection with interrupt generation ? parity control synchronous communication ? full duplex synchronous transfers ? spi master operation ? 8-bit data communication ? maximum speed: 1 mbit/s at 16 mhz (f cpu /16) lin master mode ? emission: generates 13-bit synch break frame ? reception: detects 1 1-bit break frame lin slave mode ? autonomous header handling - one single interrupt per valid message header ? automatic baud rate synchronization - maximum tolerated initial clock deviation 15 % ? synch delimiter checking ? 1 1-bit lin synch break detection - break detection always active ? parity check on the lin identifier field ? lin error management ? hot plugging support spi 4.14.2 ? maximum speed: 8 mbit/s (f master /2) both for master and slave ? full duplex synchronous transfers ? simplex synchronous transfers on two lines with a possible bidirectional data line ? master or slave operation - selectable by hardware or software ? crc calculation ? 1 byte tx and rx buf fer ? slave/master selection input pin 17 / 103 docid022186 rev 3 product overview stm8s005k6 stm8s005c6
i2c 4.14.3 ? i2c master features: - clock generation - start and stop generation ? i2c slave features: - programmable i2c address detection - stop bit detection ? generation and detection of 7-bit/10-bit addressing and general call ? supports dif ferent communication speeds: - standard speed (up to 100 khz) - fast speed (up to 400 khz) docid022186 rev 3 18 / 103 stm8s005k6 stm8s005c6 product overview
pinout and pin description 5 t able 4: legend/abbreviations for pinout tables i= input, o = output, s = power supply t ype cm = cmos input level hs = high sink output o1 = slow (up to 2 mhz) output speed o2 = fast (up to 10 mhz) o3 = fast/slow programmability with slow as default state after reset o4 = fast/slow programmability with fast as default state after reset float = floating, wpu = weak pull-up input port and control configuration t = t rue open drain, od = open drain, pp = push pull output bold x (pin state after internal reset release). reset state unless otherwise specified, the pin state is the same during the reset phase and after the internal reset release. 19 / 103 docid022186 rev 3 pinout and pin description stm8s005k6 stm8s005c6
stm8s005 pinouts and pin description 5.1 figure 3: lqfp 48-pin pinout 1. (hs) high sink capability . 2. (t) t rue open drain (p-buf fer and protection diode to v dd not implemented). 3. [ ] alternate function remapping option (if the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). docid022186 rev 3 20 / 103 stm8s005k6 stm8s005c6 pinout and pin description 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 48 47 46 45 (hs) p a6 ain8/pe7 pc1 (hs) /tim1_ch1/ u ar t2_ck pe5/spi_nss pg1 ain9/pe6 pd3 (hs) /tim2_ch2 [adc_etr] pd2 (hs) /tim3_ch1 [tim2_ch3] pe0 (hs) /clk_cco pe1 (t)/i 2 c_scl pe2 (t)/i 2 c_sd a pe3/tim1_bkin pd7/tli [tim1_ch4] pd6/u ar t2_rx pd5/u ar t2_tx pd4 (hs) /tim2_ch1 [beep] pd1 (hs) /swim pd0 (hs) /tim3_ch2 [ tim1_bkin] [clk_cco] v ssio_2 pc5 (hs) /spi_sck pc4 (hs) /tim1_ch4 pc3 (hs) /tim1_ch3 p c2 (hs) /tim1_ch2 pg0 pc7 (hs) /spi_miso pc6 (hs) /spi_mosi v ddio_2 ain7/pb7 ain6/pb6 [i 2 c_sd a] ain5/pb5 [i 2 c_scl] ain4/pb4 [tim1_etr/ain3/pb3 [tim1_ch3n] ain2/pb2 [tim1_ch2n] ain1/pb1 [tim1_ch1n] ain0/pb0 v dd a v ssa v ss vcap v dd v ddio_1 [tim3_ch1] tim2_ch3/p a3 (hs) p a4 (hs) p a5 nrst oscin/p a1 oscout/p a2 v ssio_1
figure 4: lqfp 32-pin pinout 1. (hs) high sink capability . 2. [ ] alternate function remapping option (if the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). t able 5: pin description for stm8s005 microcontrollers alternate function after remap [option bit] default alternate function main function (after reset) output input t ype pin name pin number pp od speed high sink ext. interrupt wpu floating lqfp32 lqfp48 reset x i/o nrst 1 1 resonator/ port a1 x x o1 x x i/o p a1/ osc in 2 2 crystal in resonator/ port a2 x x o1 x x x i/o p a2/ osc out 3 3 crystal out i/o ground s v ssio_1 - 4 digital ground s v ss 4 5 21 / 103 docid022186 rev 3 pinout and pin description stm8s005k6 stm8s005c6 [i 2 c_scl] ain4/pb4 [tim1_etr] ain3/pb3 [tim1_ch3n] ain2/pb2 [tim1_ch2n] ain1/pb1 [tim1_ch1n] ain0/pb0 v dd a v ssa [i 2 c_sd a] ain5/pb5 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 vcap v dd v ddio ain12/pf4 nrst oscin/p a1 oscout/p a2 v ss pc3 (hs) /tim1_ch3 pc2 (hs) /tim1_ch2 pc1 (hs) /tim1_ch1/u ar t2_ck pe5/spi_nss pc7 (hs)/spi_miso pc6 (hs)/spi_mosi pc5 (hs)/spi_sck pc4 (hs) /tim1_ch4 pd3 (hs)/tim2_ch2 [adc_etr] pd2 (hs)/tim3_ch1[tim2_ch3] pd1 (hs)/swim pd0 (hs)/tim3_ch2 [tim1_bkin] [clk_cco] pd7/tli [ tim1_ch4] pd6/u ar t 2 _rx pd5/u ar t 2 _tx pd4 (hs)/tim2_ch1 [beep]
alternate function after remap [option bit] default alternate function main function (after reset) output input t ype pin name pin number pp od speed high sink ext. interrupt wpu floating lqfp32 lqfp48 1.8 v regulator capacitor s vcap 5 6 digital power supply s v dd 6 7 i/o power supply s v ddio_1 7 8 tim3_ ch1 [afr1] t imer 2 - channel 3 port a3 x x o1 x x x i/o p a3/ tim2 _ch3 [tim3 _ch1] - 9 port a4 x x o3 hs x x x i/o p a4 - 10 port a5 x x o3 hs x x x i/o p a5 - 1 1 port a6 x x o3 hs x x x i/o p a6 - 12 analog input 12 (2) port f4 x x o1 x x i/o pf4/ ain12 (1) 8 - analog power supply s v dda 9 13 analog ground s v ssa 10 14 analog input 7 port b7 x x o1 x x x i/o pb7/ ain7 - 15 analog input 6 port b6 x x o1 x x x i/o pb6/ ain6 - 16 i 2 c_sda [afr6] analog input 5 port b5 x x o1 x x x i/o pb5/ ain5 [i 2 c_ sda] 1 1 17 i 2 c_scl [afr6] analog input 4 port b4 x x o1 x x x i/o pb4/ ain4 [i 2 c_ scl] 12 18 tim1_ etr [afr5] analog input 3 port b3 x x o1 x x x i/o pb3/ ain3 [tim1_ etr] 13 19 tim1_ ch3n [afr5] analog input 2 port b2 x x o1 x x x i/o pb2/ ain2 [tim1_ ch3n] 14 20 tim1_ ch2n [afr5] analog input 1 port b1 x x o1 x x x i/o pb1/ ain1 [tim1_ ch2n] 15 21 tim1_ ch1n [afr5] analog input 0 port b0 x x o1 x x x i/o pb0/ ain0 [tim1_ ch1n] 16 22 analog input 8 port e7 x x o1 x x x i/o pe7/ ain8 - 23 analog input 9 port e6 x x o1 x x x i/o pe6/ ain9 - 24 docid022186 rev 3 22 / 103 stm8s005k6 stm8s005c6 pinout and pin description
alternate function after remap [option bit] default alternate function main function (after reset) output input t ype pin name pin number pp od speed high sink ext. interrupt wpu floating lqfp32 lqfp48 spi master/slave select port e5 x x o1 x x x i/o pe5/spi_ nss 17 25 t imer 1 - port c1 x x o3 hs x x x i/o pc1/ tim1_ 18 26 channel 1/ uar t2 synchronous clock ch1/ uar t2_ck t imer 1- port c2 x x o3 hs x x x i/o pc2/ tim1_ ch2 19 27 channel 2 t imer 1 - port c3 x x o3 hs x x x i/o pc3/ tim1_ ch3 20 28 channel 3 t imer 1 - port c4 x x o3 hs x x x i/o pc4/ tim1_ ch4 21 29 channel 4 spi clock port c5 x x o3 hs x x x i/o pc5/ spi_ sck 22 30 i/o ground s v ssio_2 - 31 i/o power supply s v ddio_2 - 32 spi master out/slave in port c6 x x o3 hs x x x i/o pc6/ spi_ mosi 23 33 spi master in/ slave out port c7 x x o3 hs x x x i/o pc7/ spi_ miso 24 34 port g0 x x o1 x x i/o pg0 - 35 port g1 x x o1 x x i/o pg1 - 36 t imer 1 - break input port e3 x x o1 x x x i/o pe3/ tim1_ bkin - 37 i 2 c data port e2 t (3) o1 x x i/o pe2/ i 2 c_ sda - 38 i 2 c clock port e1 t (3) o1 x x i/o pe1/ i 2 c_ scl - 39 configurable clock output port e0 x x o3 hs x x x i/o pe0/ clk_ cco - 40 tim1_ bkin [afr3]/ clk_ cco [afr2] t imer 3 - channel 2 port d0 x x o3 hs x x x i/o pd0/ tim3_ ch2 [tim1_ 25 41 bkin] [clk_ cco] 23 / 103 docid022186 rev 3 pinout and pin description stm8s005k6 stm8s005c6
alternate function after remap [option bit] default alternate function main function (after reset) output input t ype pin name pin number pp od speed high sink ext. interrupt wpu floating lqfp32 lqfp48 swim data interface port d1 x x o4 hs x x x i/o pd1/ swim (4) 26 42 tim2_ch3 [afr1] t imer 3 - channel 1 port d2 x x o3 hs x x x i/o pd2/ tim3_ ch1 [tim2_ ch3] 27 43 adc_ etr [afr0] t imer 2 - channel 2 port d3 x x o3 hs x x x i/o pd3/ tim2_ ch2 [adc_ etr] 28 44 beep output [afr7] t imer 2 - channel 1 port d4 x x o3 hs x x x i/o pd4/ tim2_ ch1 [beep] 29 45 uar t2 data transmit port d5 x x o1 x x x i/o pd5/ uar t2_ tx 30 46 uar t2 data receive port d6 x x o1 x x x i/o pd6/ uar t2_ rx 31 47 tim1_ ch4 [afr4] t op level interrupt port d7 x x o1 x x x i/o pd7/ tli [tim1_ ch4] 32 48 (1) a pull-up is applied to pf4 during the reset phase. this pin is input floating after reset release. (2) ain12 is not selectable in adc scan mode or with analog watchdog. (3) in the open-drain output column, t defines a true open-drain i/o (p-buf fer , weak pull-up, and protection diode to v dd are not implemented). (4) the pd1 pin is in input pull-up during the reset phase and after internal reset release. alternate function remapping 5.1.1 as shown in the rightmost column of the pin description table, some alternate functions can be remapped at dif ferent i/o ports by programming one of eight afr (alternate function remap) option bits. when the remapping option is active, the default alternate function is no longer available. t o use an alternate function, the corresponding peripheral must be enabled in the peripheral registers. alternate function remapping does not ef fect gpio capabilities of the i/o ports (see the gpio section of the family reference manual, rm0016). docid022186 rev 3 24 / 103 stm8s005k6 stm8s005c6 pinout and pin description
memory and register map 6 memory map 6.1 figure 5: memory map the following table lists the boundary addresses for each memory size. the top of the stack is at the ram end address in each case. 25 / 103 docid022186 rev 3 memory and register map stm8s005k6 stm8s005c6 0x00 ffff flash prog r am memor y (32 kb ytes) 0x00 8000 reser v ed 0x01 0000 0x02 7fff 0x00 0000 ram 0x00 07ff (2 kb ytes) ? ? 0x00 4000 0x00 407f 128-b yte data eepr om reser v ed reser v ed 0x00 4080 0x00 47ff 32 interr upt v ectors 0x00 807f gpio and per iph. reg. 0x 00 5000 0x 00 57ff 0x 00 5800 0x 00 7fff 0x 00 4900 0x 00 4fff 2 kb ytes boot r om 0x 00 6000 0x 00 67ff 0x 00 6800 0x 00 7eff cpu/swim/deb ug/itc registers 0x 00 7f00 0x 00 5fff reser v ed reser v ed reser v ed option b ytes 0x 00 4800 0x 00 48 7f 512 b ytes stac k
t able 6: flash, data eeprom and ram boundary addresses end address start address size (bytes) memory area 0x00 ffff 0x00 8000 32k flash program memory 0x00 07ff 0x00 0000 2k ram 0x00 407f 0x00 4000 128 data eeprom register map 6.2 i/o port hardware register map 6.2.1 t able 7: i/o port hardware register map reset status register name register label block address 0x00 port a data output latch register p a_odr port a 0x00 5000 0xxx (1) port a input pin value register p a_idr 0x00 5001 0x00 port a data direction register p a_ddr 0x00 5002 0x00 port a control register 1 p a_cr1 0x00 5003 0x00 port a control register 2 p a_cr2 0x00 5004 0x00 port b data output latch register pb_odr port b 0x00 5005 0xxx (1) port b input pin value register pb_idr 0x00 5006 0x00 port b data direction register pb_ddr 0x00 5007 0x00 port b control register 1 pb_cr1 0x00 5008 0x00 port b control register 2 pb_cr2 0x00 5009 0x00 port c data output latch register pc_odr port c 0x00 500a docid022186 rev 3 26 / 103 stm8s005k6 stm8s005c6 memory and register map
reset status register name register label block address 0xxx (1) port c input pin value register pc_idr 0x00 500b 0x00 port c data direction register pc_ddr 0x00 500c 0x00 port c control register 1 pc_cr1 0x00 500d 0x00 port c control register 2 pc_cr2 0x00 500e 0x00 port d data output latch register pd_odr port d 0x00 500f 0xxx (1) port d input pin value register pd_idr 0x00 5010 0x00 port d data direction register pd_ddr 0x00 501 1 0x02 port d control register 1 pd_cr1 0x00 5012 0x00 port d control register 2 pd_cr2 0x00 5013 0x00 port e data output latch register pe_odr port e 0x00 5014 0xxx (1) port e input pin value register pe_idr 0x00 5015 0x00 port e data direction register pe_ddr 0x00 5016 0x00 port e control register 1 pe_cr1 0x00 5017 0x00 port e control register 2 pe_cr2 0x00 5018 0x00 port f data output latch register pf_odr port f 0x00 5019 0xxx (1) port f input pin value register pf_idr 0x00 501a 0x00 port f data direction register pf_ddr 0x00 501b 0x00 port f control register 1 pf_cr1 0x00 501c 0x00 port f control register 2 pf_cr2 0x00 501d 27 / 103 docid022186 rev 3 memory and register map stm8s005k6 stm8s005c6
reset status register name register label block address 0x00 port g data output latch register pg_odr port g 0x00 501e 0xxx (1) port g input pin value register pg_idr 0x00 501f 0x00 port g data direction register pg_ddr 0x00 5020 0x00 port g control register 1 pg_cr1 0x00 5021 0x00 port g control register 2 pg_cr2 0x00 5022 0x00 port h data output latch register ph_odr port h 0x00 5023 0xxx (1) port h input pin value register ph_idr 0x00 5024 0x00 port h data direction register ph_ddr 0x00 5025 0x00 port h control register 1 ph_cr1 0x00 5026 0x00 port h control register 2 ph_cr2 0x00 5027 0x00 port i data output latch register pi_odr port i 0x00 5028 0xxx (1) port i input pin value register pi_idr 0x00 5029 0x00 port i data direction register pi_ddr 0x00 502a 0x00 port i control register 1 pi_cr1 0x00 502b 0x00 port i control register 2 pi_cr2 0x00 502c (1) depends on the external circuitry . docid022186 rev 3 28 / 103 stm8s005k6 stm8s005c6 memory and register map
general hardware register map 6.2.2 t able 8: general hardware register map reset status register name register label block address reserved area (10 bytes) 0x00 5050 to 0x00 5059 0x00 flash control register 1 flash_cr1 flash 0x00 505a 0x00 flash control register 2 flash_cr2 0x00 505b 0xff flash complementary control register 2 flash_ncr2 0x00 505c 0x00 flash protection register flash _fpr 0x00 505d 0xff flash complementary protection register flash _nfpr 0x00 505e 0x00 flash in-application programming status register flash _iapsr 0x00 505f reserved area (2 bytes) 0x00 5060 to 0x00 5061 0x00 flash program memory unprotection register flash _pukr flash 0x00 5062 reserved area (1 byte) 0x00 5063 0x00 data eeprom unprotection register flash _dukr flash 0x00 5064 reserved area (59 bytes) 0x00 5065 to 0x00 509f 0x00 external interrupt control register 1 exti_cr1 itc 0x00 50a0 0x00 external interrupt control register 2 exti_cr2 0x00 50a1 reserved area (17 bytes) 0x00 50a2 to 0x00 50b2 29 / 103 docid022186 rev 3 memory and register map stm8s005k6 stm8s005c6
reset status register name register label block address 0xxx (1) reset status register rst_sr rst 0x00 50b3 reserved area (12 bytes) 0x00 50b4 to 0x00 50bf 0x01 internal clock control register clk_ickr clk 0x00 50c0 0x00 external clock control register clk_eckr 0x00 50c1 reserved area (1 byte) 0x00 50c2 0xe1 clock master status register clk_cmsr clk 0x00 50c3 0xe1 clock master switch register clk_swr 0x00 50c4 0xxx clock switch control register clk_swcr 0x00 50c5 0x18 clock divider register clk_ckdivr 0x00 50c6 0xff peripheral clock gating register 1 clk_pckenr1 0x00 50c7 0x00 clock security system register clk_cssr 0x00 50c8 0x00 configurable clock control register clk_ccor 0x00 50c9 0xff peripheral clock gating register 2 clk_pckenr2 0x00 50ca 0x00 hsi clock calibration trimming register clk_hsitrimr 0x00 50cc 0bxxxx xxx0 swim clock control register clk_swimccr 0x00 50cd reserved area (3 bytes) 0x00 50ce to 0x00 50d0 0x7f wwdg control register wwdg_cr wwdg 0x00 50d1 0x7f wwdr window register wwdg_wr 0x00 50d2 docid022186 rev 3 30 / 103 stm8s005k6 stm8s005c6 memory and register map
reset status register name register label block address reserved area (13 bytes) 0x00 50d3 to 0x00 50df 0xxx (2) iwdg key register iwdg_kr iwdg 0x00 50e0 0x00 iwdg prescaler register iwdg_pr 0x00 50e1 0xff iwdg reload register iwdg_rlr 0x00 50e2 reserved area (13 bytes) 0x00 50e3 to 0x00 50ef 0x00 a wu control/ status register 1 a wu_csr1 a wu 0x00 50f0 0x3f a wu asynchronous prescaler buf fer register a wu_apr 0x00 50f1 0x00 a wu timebase selection register a wu_tbr 0x00 50f2 0x1f beep control/ status register beep_csr beep 0x00 50f3 reserved area (12 bytes) 0x00 50f4 to 0x00 50ff 0x00 spi control register 1 spi_cr1 spi 0x00 5200 0x00 spi control register 2 spi_cr2 0x00 5201 0x00 spi interrupt control register spi_icr 0x00 5202 0x02 spi status register spi_sr 0x00 5203 0x00 spi data register spi_dr 0x00 5204 0x07 spi crc polynomial register spi_crcpr 0x00 5205 0xff spi rx crc register spi_rxcrcr 0x00 5206 0xff spi tx crc register spi_txcrcr 0x00 5207 31 / 103 docid022186 rev 3 memory and register map stm8s005k6 stm8s005c6
reset status register name register label block address reserved area (8 bytes) 0x00 5208 to 0x00 520f 0x00 i 2 c control register 1 i2c_cr1 i 2 c 0x00 5210 0x00 i 2 c control register 2 i2c_cr2 0x00 521 1 0x00 i 2 c frequency register i2c_freqr 0x00 5212 0x00 i 2 c own address register low i2c_oarl 0x00 5213 0x00 i 2 c own address register high i2c_oarh 0x00 5214 reserved 0x00 5215 0x00 i 2 c data register i2c_dr 0x00 5216 0x00 i 2 c status register 1 i2c_sr1 0x00 5217 0x00 i 2 c status register 2 i2c_sr2 0x00 5218 0x00 i 2 c status register 3 i2c_sr3 0x00 5219 0x00 i 2 c interrupt control register i2c_itr 0x00 521a 0x00 i 2 c clock control register low i2c_ccrl 0x00 521b 0x00 i 2 c clock control register high i2c_ccrh 0x00 521c 0x02 i 2 c trise register i2c_triser 0x00 521d 0x00 i 2 c packet error checking register i2c_pecr 0x00 521e reserved area (17 bytes) 0x00 521f to 0x00 522f reserved area (6 bytes) 0x00 5230 to 0x00 523f docid022186 rev 3 32 / 103 stm8s005k6 stm8s005c6 memory and register map
reset status register name register label block address 0xc0 uar t2 status register uar t2_sr uar t2 0x00 5240 0xxx uar t2 data register uar t2_dr 0x00 5241 0x00 uar t2 baud rate register 1 uar t2_brr1 0x00 5242 0x00 uar t2 baud rate register 2 uar t2_brr2 0x00 5243 0x00 uar t2 control register 1 uar t2_cr1 0x00 5244 0x00 uar t2 control register 2 uar t2_cr2 0x00 5245 0x00 uar t2 control register 3 uar t2_cr3 0x00 5246 0x00 uar t2 control register 4 uar t2_cr4 0x00 5247 0x00 uar t2 control register 5 uar t2_cr5 0x00 5248 0x00 uar t2 control register 6 uar t2_cr6 0x00 5249 0x00 uar t2 guard time register uar t2_gtr 0x00 524a 0x00 uar t2 prescaler register uar t2_pscr 0x00 524b reserved area (4 bytes) 0x00 524c to 0x00 524f 0x00 tim1 control register 1 tim1_cr1 tim1 0x00 5250 0x00 tim1 control register 2 tim1_cr2 0x00 5251 0x00 tim1 slave mode control register tim1_smcr 0x00 5252 0x00 tim1 external trigger register tim1_etr 0x00 5253 0x00 tim1 interrupt enable register tim1_ier 0x00 5254 0x00 tim1 status register 1 tim1_sr1 0x00 5255 33 / 103 docid022186 rev 3 memory and register map stm8s005k6 stm8s005c6
reset status register name register label block address 0x00 tim1 status register 2 tim1_sr2 0x00 5256 0x00 tim1 event generation register tim1_egr 0x00 5257 0x00 tim1 capture/ compare mode register 1 tim1_ccmr1 0x00 5258 0x00 tim1 capture/compare mode register 2 tim1_ccmr2 0x00 5259 0x00 tim1 capture/ compare mode register 3 tim1_ccmr3 0x00 525a 0x00 tim1 capture/compare mode register 4 tim1_ccmr4 0x00 525b 0x00 tim1 capture/ compare enable register 1 tim1_ccer1 0x00 525c 0x00 tim1 capture/compare enable register 2 tim1_ccer2 0x00 525d 0x00 tim1 counter high tim1_cntrh 0x00 525e 0x00 tim1 counter low tim1_cntrl 0x00 525f 0x00 tim1 prescaler register high tim1_pscrh 0x00 5260 0x00 tim1 prescaler register low tim1_pscrl 0x00 5261 0xff tim1 auto-reload register high tim1_arrh 0x00 5262 0xff tim1 auto-reload register low tim1_arrl 0x00 5263 0x00 tim1 repetition counter register tim1_rcr 0x00 5264 0x00 tim1 capture/ compare register 1 high tim1_ccr1h 0x00 5265 docid022186 rev 3 34 / 103 stm8s005k6 stm8s005c6 memory and register map
reset status register name register label block address 0x00 tim1 capture/ compare register 1 low tim1_ccr1l 0x00 5266 0x00 tim1 capture/ compare register 2 high tim1_ccr2h 0x00 5267 0x00 tim1 capture/ compare register 2 low tim1_ccr2l 0x00 5268 0x00 tim1 capture/ compare register 3 high tim1_ccr3h 0x00 5269 0x00 tim1 capture/ compare register 3 low tim1_ccr3l 0x00 526a 0x00 tim1 capture/ compare register 4 high tim1_ccr4h 0x00 526b 0x00 tim1 capture/ compare register 4 low tim1_ccr4l 0x00 526c 0x00 tim1 break register tim1_bkr 0x00 526d 0x00 tim1 dead-time register tim1_dtr 0x00 526e 0x00 tim1 output idle state register tim1_oisr 0x00 526f reserved area (147 bytes) 0x00 5270 to 0x00 52ff 0x00 tim2 control register 1 tim2_cr1 tim2 0x00 5300 0x00 tim2 interrupt enable register tim2_ier 0x00 5301 0x00 tim2 status register 1 tim2_sr1 0x00 5302 0x00 tim2 status register 2 tim2_sr2 0x00 5303 0x00 tim2 event generation register tim2_egr 0x00 5304 0x00 tim2 capture/ compare mode register 1 tim2_ccmr1 0x00 5305 0x00 tim2 capture/ compare mode register 2 tim2_ccmr2 0x00 5306 35 / 103 docid022186 rev 3 memory and register map stm8s005k6 stm8s005c6
reset status register name register label block address 0x00 tim2 capture/ compare mode register 3 tim2_ccmr3 0x00 5307 0x00 tim2 capture/ compare enable register 1 tim2_ccer1 0x00 5308 0x00 tim2 capture/ compare enable register 2 tim2_ccer2 0x00 5309 0x00 tim2 counter high tim2_cntrh 0x00 530a 0x00 tim2 counter low tim2_cntrl 0x00 530b 0x00 tim2 prescaler register tim2_pscr 0x00 530c 0xff tim2 auto-reload register high tim2_arrh 0x00 530d 0xff tim2 auto-reload register low tim2_arrl 0x00 530e 0x00 tim2 capture/ compare register 1 high tim2_ccr1h 0x00 530f 0x00 tim2 capture/ compare register 1 low tim2_ccr1l 0x00 5310 0x00 tim2 capture/ compare reg. 2 high tim2_ccr2h 0x00 531 1 0x00 tim2 capture/ compare register 2 low tim2_ccr2l 0x00 5312 0x00 tim2 capture/ compare register 3 high tim2_ccr3h 0x00 5313 0x00 tim2 capture/ compare register 3 low tim2_ccr3l 0x00 5314 reserved area (1 1 bytes) 0x00 5315 to 0x00 531f 0x00 tim3 control register 1 tim3_cr1 tim3 0x00 5320 0x00 tim3 interrupt enable register tim3_ier 0x00 5321 0x00 tim3 status register 1 tim3_sr1 0x00 5322 docid022186 rev 3 36 / 103 stm8s005k6 stm8s005c6 memory and register map
reset status register name register label block address 0x00 tim3 status register 2 tim3_sr2 0x00 5323 0x00 tim3 event generation register tim3_egr 0x00 5324 0x00 tim3 capture/ compare mode register 1 tim3_ccmr1 0x00 5325 0x00 tim3 capture/ compare mode register 2 tim3_ccmr2 0x00 5326 0x00 tim3 capture/ compare enable register 1 tim3_ccer1 0x00 5327 0x00 tim3 counter high tim3_cntrh 0x00 5328 0x00 tim3 counter low tim3_cntrl 0x00 5329 0x00 tim3 prescaler register tim3_pscr 0x00 532a 0xff tim3 auto-reload register high tim3_arrh 0x00 532b 0xff tim3 auto-reload register low tim3_arrl 0x00 532c 0x00 tim3 capture/ compare register 1 high tim3_ccr1h 0x00 532d 0x00 tim3 capture/ compare register 1 low tim3_ccr1l 0x00 532e 0x00 tim3 capture/ compare register 2 high tim3_ccr2h 0x00 532f 0x00 tim3 capture/ compare register 2 low tim3_ccr2l 0x00 5330 reserved area (15 bytes) 0x00 5331 to 0x00 533f 0x00 tim4 control register 1 tim4_cr1 tim4 0x00 5340 0x00 tim4 interrupt enable register tim4_ier 0x00 5341 0x00 tim4 status register tim4_sr 0x00 5342 37 / 103 docid022186 rev 3 memory and register map stm8s005k6 stm8s005c6
reset status register name register label block address 0x00 tim4 event generation register tim4_egr 0x00 5343 0x00 tim4 counter tim4_cntr 0x00 5344 0x00 tim4 prescaler register tim4_pscr 0x00 5345 0xff tim4 auto-reload register tim4_arr 0x00 5346 reserved area (153 bytes) 0x00 5347 to 0x00 53df 0x00 adc data buf fer registers adc _dbxr adc1 0x00 53e0 to 0x00 53f3 reserved area (12 bytes) 0x00 53f4 to 0x00 53ff 0x00 adc control/ status register adc _csr adc1 0x00 5400 0x00 adc configuration register 1 adc_cr1 0x00 5401 0x00 adc configuration register 2 adc_cr2 0x00 5402 0x00 adc configuration register 3 adc_cr3 0x00 5403 0xxx adc data register high adc_drh 0x00 5404 0xxx adc data register low adc_drl 0x00 5405 0x00 adc schmitt trigger disable register high adc_tdrh 0x00 5406 0x00 adc schmitt trigger disable register low adc_tdrl 0x00 5407 0x03 adc high threshold register high adc_htrh 0x00 5408 0xff adc high threshold register low adc_htrl 0x00 5409 docid022186 rev 3 38 / 103 stm8s005k6 stm8s005c6 memory and register map
reset status register name register label block address 0x00 adc low threshold register high adc_l trh 0x00 540a 0x00 adc low threshold register low adc_l trl 0x00 540b 0x00 adc analog watchdog status register high adc_a wsrh 0x00 540c 0x00 adc analog watchdog status register low adc_a wsrl 0x00 540d 0x00 adc analog watchdog control register high adc _a wcrh 0x00 540e 0x00 adc analog watchdog control register low adc_a wcrl 0x00 540f reserved area (1008 bytes) 0x00 5410 to 0x00 57ff (1) depends on the previous reset source. (2) w rite only register . cpu/swim/debug module/interrupt controller registers 6.2.3 t able 9: cpu/swim/debug module/interrupt controller registers reset status register name register label block address 0x00 accumulator a cpu (1) 0x00 7f00 0x00 program counter extended pce 0x00 7f01 0x00 program counter high pch 0x00 7f02 0x00 program counter low pcl 0x00 7f03 0x00 x index register high xh 0x00 7f04 39 / 103 docid022186 rev 3 memory and register map stm8s005k6 stm8s005c6
reset status register name register label block address 0x00 x index register low xl 0x00 7f05 0x00 y index register high yh 0x00 7f06 0x00 y index register low yl 0x00 7f07 0x07 stack pointer high sph 0x00 7f08 0xff stack pointer low spl 0x00 7f09 0x28 condition code register ccr 0x00 7f0a reserved area (85 bytes) 0x00 7f0b to 0x00 7f5f 0x00 global configuration register cfg_gcr cpu 0x00 7f60 0xff interrupt software priority register 1 itc_spr1 itc 0x00 7f70 0xff interrupt software priority register 2 itc_spr2 0x00 7f71 0xff interrupt software priority register 3 itc_spr3 0x00 7f72 0xff interrupt software priority register 4 itc_spr4 0x00 7f73 0xff interrupt software priority register 5 itc_spr5 0x00 7f74 0xff interrupt software priority register 6 itc_spr6 0x00 7f75 0xff interrupt software priority register 7 itc_spr7 0x00 7f76 0xff interrupt software priority register 8 itc_spr8 0x00 7f77 reserved area (2 bytes) 0x00 7f78 to 0x00 7f79 0x00 swim control status register swim_csr swim 0x00 7f80 docid022186 rev 3 40 / 103 stm8s005k6 stm8s005c6 memory and register map
reset status register name register label block address reserved area (15 bytes) 0x00 7f81 to 0x00 7f8f 0xff dm breakpoint 1 register extended byte dm_bk1re dm 0x00 7f90 0xff dm breakpoint 1 register high byte dm_bk1rh 0x00 7f91 0xff dm breakpoint 1 register low byte dm_bk1rl 0x00 7f92 0xff dm breakpoint 2 register extended byte dm_bk2re 0x00 7f93 0xff dm breakpoint 2 register high byte dm_bk2rh 0x00 7f94 0xff dm breakpoint 2 register low byte dm_bk2rl 0x00 7f95 0x00 dm debug module control register 1 dm_cr1 0x00 7f96 0x00 dm debug module control register 2 dm_cr2 0x00 7f97 0x10 dm debug module control/status register 1 dm_csr1 0x00 7f98 0x00 dm debug module control/status register 2 dm_csr2 0x00 7f99 0xff dm enable function register dm_enfctr 0x00 7f9a reserved area (5 bytes) 0x00 7f9b to 0x00 7f9f (1) accessible by debug module only 41 / 103 docid022186 rev 3 memory and register map stm8s005k6 stm8s005c6
interrupt vector mapping 7 t able 10: interrupt mapping v ector address w akeup from active-halt mode w akeup from halt mode description source block irq no. 0x00 8000 y es y es reset reset 0x00 8004 - - software interrupt trap 0x00 8008 - - external top level interrupt tli 0 0x00 800c y es - auto wake up from halt a wu 1 0x00 8010 - - clock controller clk 2 0x00 8014 y es (1) y es (1) port a external interrupts exti0 3 0x00 8018 y es y es port b external interrupts exti1 4 0x00 801c y es y es port c external interrupts exti2 5 0x00 8020 y es y es port d external interrupts exti3 6 0x00 8024 y es y es port e external interrupts exti4 7 0x00 8028 8 0x00 802c - - reserved 9 0x00 8030 y es y es end of transfer spi 10 0x00 8034 - - tim1 update/ overflow/ underflow/ trigger/ break tim1 1 1 0x00 8038 - - tim1 capture/ compare tim1 12 0x00 803c - - tim update/ overflow tim 13 0x00 8040 - - tim capture/ compare tim 14 docid022186 rev 3 42 / 103 stm8s005k6 stm8s005c6 interrupt vector mapping
v ector address w akeup from active-halt mode w akeup from halt mode description source block irq no. 0x00 8044 - - update/ overflow tim3 15 0x00 8048 - - capture/ compare tim3 16 0x00 804c - - reserved 17 0x00 8050 - - reserved 18 0x00 8054 y es y es i 2 c interrupt i 2 c 19 0x00 8058 - - tx complete uar t2 20 0x00 805c - - receive register da t a full uar t2 21 0x00 8060 - - adc1 end of conversion/ analog watchdog interrupt adc1 22 0x00 8064 - - tim update/ overflow tim 23 0x00 8068 - - eop/ wr_pg_dis flash 24 0x00 806c to 0x00 807c reserved (1) except p a1 43 / 103 docid022186 rev 3 interrupt vector mapping stm8s005k6 stm8s005c6
option bytes 8 option bytes contain configurations for device hardware features as well as the memory protection of the device. they are stored in a dedicated block of the memory . except for the rop (read-out protection) byte, each option byte has to be stored twice, in a regular form (optx) and a complemented one (noptx) for redundancy . option bytes can be modified in icp mode (via swim) by accessing the eeprom address shown in the table below . option bytes can also be modified on the fly by the application in iap mode, except the rop option that can only be modified in icp mode (via swim). refer to the stm8s flash programming manual (pm0051) and stm8 swim communication protocol and debug module user manual (um0470) for information on swim programming procedures. t able 1 1: option bytes factory default setting option bits option byte no. option name addr . 0 1 2 3 4 5 6 7 00h rop [7:0] opt0 read-out protection (rop) 0x4800 00h ubc [7:0] opt1 user boot code(ubc) 0x4801 ffh nubc [7:0] nopt1 0x4802 00h afr0 afr1 afr2 afr3 afr4 afr5 afr6 afr7 opt2 alternate function 0x4803 ffh nafr0 nafr1 nafr2 nafr3 nafr4 nafr5 nafr6 nafr7 nopt2 0x4804 remapping (afr) 00h wwdg _hal t wwdg _hw iwdg _hw lsi_ en hsi trim reserved opt3 miscell. option 0x4805h ffh nww g_hal t nwwdg _hw niwdg _hw nlsi_ en nhsi trim reserved nopt3 0x4806 00h prs c0 prs c1 cka wu sel ext clk reserved opt4 clock option 0x4807 ffh npr sc0 nprsc1 ncka wusel next clk reserved nopt4 0x4808 00h hsecnt [7:0] opt5 hse clock startup 0x4809 ffh nhsecnt [7:0] nopt5 0x480a 00h reserved opt6 reserved 0x480b docid022186 rev 3 44 / 103 stm8s005k6 stm8s005c6 option bytes
factory default setting option bits option byte no. option name addr . 0 1 2 3 4 5 6 7 ffh reserved nopt6 0x480c 00h reserved opt7 reserved 0x480d ffh reserved nopt7 0x480e 00h bl[7:0] optbl bootloader 0x487e ffh nbl[7:0] noptbl 0x487f t able 12: option byte description description option byte no. rop[7:0] memory readout protection (rop) opt0 aah: enable readout protection (write access via swim protocol) note: refer to the family reference manual (rm0016) section on flash/eeprom memory readout protection for details. ubc[7:0] user boot code area opt1 0x00: no ubc, no write-protection 0x01: page 0 to 1 defined as ubc, memory write-protected 0x02: page 0 to 3 defined as ubc, memory write-protected 0x03: page 0 to 4 defined as ubc, memory write-protected ... 0x3e: pages 0 to 63 defined as ubc, memory write-protected other values: reserved note: refer to the family reference manual (rm0016) section on flash write protection for more details. afr[7:0] opt2 refer to following table for the alternate function remapping decriptions of bits [7:2]. hsitrim :high speed internal clock trimming register size opt3 0: 3-bit trimming supported in clk_hsitrimr register 1: 4-bit trimming supported in clk_hsitrimr register 45 / 103 docid022186 rev 3 option bytes stm8s005k6 stm8s005c6
description option byte no. lsi_en :low speed internal clock enable 0: lsi clock is not available as cpu clock source 1: lsi clock is available as cpu clock source iwdg_hw : independent watchdog 0: iwdg independent watchdog activated by software 1: iwdg independent watchdog activated by hardware wwdg_hw : window watchdog activation 0: wwdg window watchdog activated by software 1: wwdg window watchdog activated by hardware wwdg_hal t : window watchdog reset on halt 0: no reset generated on halt if wwdg active 1: reset generated on halt if wwdg active extclk : external clock selection opt4 0: external crystal connected to oscin/oscout 1: external clock signal on oscin cka wusel :auto wake-up unit/clock 0: lsi clock source selected for a wu 1: hse clock with prescaler selected as clock source for for a wu prsc[1:0] a wu clock prescaler 0x: 16 mhz to 128 khz prescaler 10: 8 mhz to 128 khz prescaler 1 1: 4 mhz to 128 khz prescaler hsecnt[7:0] :hse crystal oscillator stabilization time opt5 0x00: 2048 hse cycles 0xb4: 128 hse cycles 0xd2: 8 hse cycles 0xe1: 0.5 hse cycles docid022186 rev 3 46 / 103 stm8s005k6 stm8s005c6 option bytes
description option byte no. reserved opt6 reserved opt7 bl[7:0] bootloader option byte optbl for stm8s products, this option is checked by the boot rom code after reset. depending on the content of addresses 0x487e, 0x487f , and 0x8000 (reset vector), the cpu jumps to the bootloader or to the reset vector . refer to the um0560 (stm8l/s bootloader manual) for more details. for stm8l products, the bootloader option bytes are on addresses 0xxxxx and 0xxxxx+1 (2 bytes). these option bytes control whether the bootloader is active or not. for more details, refer to the um0560 (stm8l/s bootloader manual) for more details. t able 13: description of alternate function remapping bits [7:0] of opt2 description (1) option byte no. afr7 alternate function remapping option 7 opt2 0: afr7 remapping option inactive: default alternate function (2) . 1: port d4 alternate function = beep . afr6 alternate function remapping option 6 0: afr6 remapping option inactive: default alternate functions (2) . 1: port b5 alternate function = i 2 c_sda; port b4 alternate function = i 2 c_scl. afr5 alternate function remapping option 5 0: afr5 remapping option inactive: default alternate functions (2) . 1: port b3 alternate function = tim1_etr; port b2 alternate function = tim1_ncc3; port b1 alternate function = tim1_ch2n; port b0 alternate function = tim1_ch1n. afr4 alternate function remapping option 4 0: afr4 remapping option inactive: default alternate function (2) . 1: port d7 alternate function = tim1_ch4. afr3 alternate function remapping option 3 0: afr3 remapping option inactive: default alternate function (2) . 1: port d0 alternate function = tim1_bkin. afr2 alternate function remapping option 2 47 / 103 docid022186 rev 3 option bytes stm8s005k6 stm8s005c6
description (1) option byte no. 0: afr2 remapping option inactive: default alternate function (2) . 1: port d0 alternate function = clk_cco.note: afr2 option has priority over afr3 if both are activated. afr1 alternate function remapping option 1 0: afr1 remapping option inactive: default alternate functions (2) . 1: port a3 alternate function = tim3_ch1; port d2 alternate function tim2_ch3. afr0 alternate function remapping option 0 0: afr0 remapping option inactive: default alternate function (2) . 1: port d3 alternate function = adc_etr. (1) do not use more than one remapping option in the same port. (2) refer to pinout description. docid022186 rev 3 48 / 103 stm8s005k6 stm8s005c6 option bytes
electrical characteristics 9 parameter conditions 9.1 unless otherwise specified, all voltages are referred to v ss . minimum and maximum values 9.1.1 unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100 % of the devices with an ambient temperature at t a = 25 c and t a = t amax (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean 3 ). t ypical values 9.1.2 unless otherwise specified, typical data are based on t a = 25 c, v dd = 5 v . they are given only as design guidelines and are not tested. t ypical adc accuracy values are determined by characterization of a batch of samples from a standard dif fusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean 2 ). t ypical curves 9.1.3 unless otherwise specified, all typical curves are given only as design guidelines and are not tested. t ypical current consumption 9.1.4 for typical current consumption measurements, v dd , v ddio and v dda are connected together in the configuration shown in the following figure. figure 6: supply current measurement conditions 49 / 103 docid022186 rev 3 electrical characteristics stm8s005k6 stm8s005c6 5 v or 3.3 v a v v v v v v dd dd a ddio ss ssa ssio
loading capacitor 9.1.5 the loading conditions used for pin parameter measurement are shown in the following figure. figure 7: pin loading conditions pin input voltage 9.1.6 the input voltage measurement on a pin of the device is described in the following figure. figure 8: pin input voltage absolute maximum ratings 9.2 stresses above those listed as absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may af fect device reliability . t able 14: v oltage characteristics unit max min ratings symbol v 6.5 -0.3 supply voltage (including v dda and v ddio ) (1) v ddx - v ss 6.5 v ss - 0.3 input voltage on true open drain pins (pe1, pe2) (2) v in docid022186 rev 3 50 / 103 stm8s005k6 stm8s005c6 electrical characteristics stm8 pin 50 pf stm8 pin v in
unit max min ratings symbol v dd + 0.3 v ss - 0.3 input voltage on any other pin (2) mv 50 v ariations between dif ferent power pins |v ddx - v dd | 50 v ariations between all the dif ferent ground pins |v ssx - v ss | see absolute maximum ratings (electrical sensitivity) electrostatic discharge voltage v esd (1) all power (v dd , v ddio , v dda ) and ground (v ss , v ssio , v ssa ) pins must always be connected to the external power supply (2) i inj(pin) must never be exceeded. this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current must be limited externally to the i inj(pin) value. a positive injection is induced by v in >v dd while a negative injection is induced by v in unit max. (1) ratings symbol 4 injected current on nrst pin i inj(pin) (4) (5) 4 injected current on oscin pin 4 injected current on any other pin (6) 20 t otal injected current (sum of all i/o and control pins) (6) i inj(pin) (4) (1) data based on characterization results, not tested in production. (2) all power (v dd , v ddio , v dda ) and ground (v ss , v ssio , v ssa ) pins must always be connected to the external supply . (3) i/o pins used simultaneously for high current source/sink must be uniformly spaced around the package between the v ddio /v ssio pins. (4) i inj(pin) must never be exceeded. this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current must be limited externally to the i inj(pin) value. a positive injection is induced by v in >v dd while a negative injection is induced by v in t able 17: general operating conditions unit max min conditions parameter symbol mhz 16 0 internal cpu clock frequency f cpu v 5.5 2.95 standard operating voltage v dd / v dd_io nf 3300 470 c ext : capacitance of external capacitor vcap (1) ohm 0.3 at 1 mhz (4) esr of external capacitor nh 15 esl of external capacitor mw 443 48-pin devices, with output on eight standard power dissipation at t a = 85 c for suf fix 6 p d (2) ports, two high sink ports and two open drain ports simultaneously (3) 360 32-pin package, with output on eight standard ports and two high sink ports simultaneously (3) c 85 -40 maximum power dissipation ambient temperature for 6 suf fix version t a 105 -40 6 suf fix version junction temperature range t j (1) care should be taken when selecting the capacitor , due to its tolerance, as well as the parameter dependency on temperature, dc bias and frequency in addition to other factors. the parameter maximum value must be respected for the full application range. (2) t o calculate p dmax (t a ), use the formula p dmax = (t jmax - t a )/ ja (see thermal characteristics ) with the value for t jmax given in the current table and the value for ja given in thermal characteristics . (3) refer to thermal characteristics . (4) this frequency of 1 mhz as a condition for v cap parameters is given by design of the internal regulator . 53 / 103 docid022186 rev 3 electrical characteristics stm8s005k6 stm8s005c6
figure 9: f cpumax versus v dd t able 18: operating conditions at power-up/power-down unit max t yp min conditions parameter symbol s/v 2.0 (1) v dd rise time rate t vdd 2.0 (1) v dd fall time rate ms 1.7 (1) v dd rising reset releasedelay t temp v 2.95 2.8 2.65 power-on reset threshold v it+ 2.88 2.7 2.58 brown-out reset threshold v it- mv 70 brown-out reset hysteresis v hys(bor) (1) guaranteed by design, not tested in production. vcap external capacitor 9.3.1 stabilization for the main regulator is achieved connecting an external capacitor c ext to the v cap pin. c ext is specified in the operating conditions section. care should be taken to limit the series inductance to less than 15 nh. docid022186 rev 3 54 / 103 stm8s005k6 stm8s005c6 electrical characteristics 16 12 8 4 0 2.95 4.0 5.0 5.5 f cpu (mhz) functionality guar anteed @t a -40 to 85 c supply v oltage functionality not guar anteed in this area
figure 10: external capacitor c ext 1. esr is the equivalent series resistance and esl is the equivalent inductance. supply current characteristics 9.3.2 the current consumption is measured as described in pin input voltage . t otal current consumption in run mode 9.3.2.1 t able 19: t otal current consumption with code execution in run mode at v dd = 5 v unit max (1) t yp conditions parameter symbol ma 3.2 hse crystal osc. (16 mhz) f cpu = f master = 16 mhz supply current in run mode, code i dd(run) executed from ram 3.2 2.6 hse user ext. clock (16 mhz) 3.2 2.5 hsi rc osc. (16 mhz) 2.2 1.6 hse user ext. clock (16 mhz) f cpu = f master /128 = 125 khz 2.0 1.3 hsi rc osc. (16 mhz) 0.75 hsi rc osc. (16 mh3z/8) f cpu = f master /128 = 15.625 khz 0.55 lsi rc osc. (128 khz) f cpu = f master = 128 khz 55 / 103 docid022186 rev 3 electrical characteristics stm8s005k6 stm8s005c6 esr r leak esl c
unit max (1) t yp conditions parameter symbol 7.7 hse crystal osc. (16 mhz) f cpu = f master = 16 mhz supply current in run mode, code i dd(run) executed fromflash 8.0 7.0 hse user ext. clock (16 mhz) 8.0 7.0 hsi rc osc. (16 mhz) 1.5 hsi rc osc. (16 mhz/8) (2) f cpu = f master = 2 mhz 2.0 1.35 hsi rc osc. (16 mhz) f cpu = f master /128 = 125 khz 0.75 hsi rc osc. (16 mhz/8) f cpu = f master /128 = 15.625 khz 0.6 lsi rc osc. (128 khz) f cpu = f master = 128 khz (1) data based on characterization results, not tested in production. (2) default clock configuration measured with all peripherals of f. t able 20: t otal current consumption with code execution in run mode at v dd = 3.3 v unit max (1) t yp conditions parameter symbol ma 2.8 hse crystal osc. (16 mhz) f cpu = f master = 16 mhz supply current in run i dd(run) mode, 3.2 2.6 hse user ext. clock (16 mhz) code executed from ram 3.2 2.5 hsi rc osc. (16 mhz) docid022186 rev 3 56 / 103 stm8s005k6 stm8s005c6 electrical characteristics
unit max (1) t yp conditions parameter symbol 2.2 1.6 hse user ext. clock (16 mhz) f cpu = f master /128 = 125 khz 2.0 1.3 hsi rc osc. (16 mhz) 0.75 hsi rc osc. (16 mhz/8) f cpu = f master /128 = 15.625 khz 0.55 lsi rc osc. (128 khz) f cpu = f master = 128 khz 7.3 hse crystal osc. (16 mhz) f cpu = f master = 16 mhz supply current in run mode, 8.0 7.0 hse user ext. clock (16 mhz) code executed from flash 8.0 7.0 hsi rc osc. (16 mhz) 1.5 hsi rc osc. (16 mhz/8) (2) f cpu = f master = 2 mhz 2.0 1.35 hsi rc osc. (16 mhz) f cpu = f master /128 = 125 khz 0.75 hsi rc osc. (16 mhz/8) f cpu = f master /128 = 15.625 khz 0.6 lsi rc osc. (128 khz) f cpu = f master = 128 khz (1) data based on characterization results, not tested in production. (2) default clock configuration measured with all peripherals of f. 57 / 103 docid022186 rev 3 electrical characteristics stm8s005k6 stm8s005c6
t otal current consumption in wait mode 9.3.2.2 t able 21: t otal current consumption in wait mode at v dd = 5 v unit max (1) t yp conditions parameter symbol ma 2.15 hse crystal osc. (16 mhz) f cpu = f master = 16 mhz supply current in wait mode i dd(wfi) 2.0 1.55 hse user ext. clock (16 mhz) 1.9 1.5 hsi rc osc. (16 mhz) 1.3 hsi rc osc. (16 mhz) f cpu = f master /128 = 125 khz 0.7 hsi rc osc. (16 mhz/8) (2) f cpu = f master /128 = 15.625 khz 0.5 lsi rc osc. (128 khz) f cpu = f master = 128 khz (1) data based on characterization results, not tested in production. (2) default clock configuration measured with all peripherals of f. t able 22: t otal current consumption in wait mode at v dd = 3.3 v unit max (1) t yp conditions parameter symbol ma 1.75 hse crystal osc. (16 mhz) f cpu = f master = 16 mhz supply current in wait mode i dd(wfi) 2.0 1.55 hse user ext. clock (16 mhz) 1.9 1.5 hsi rc osc. (16 mhz) docid022186 rev 3 58 / 103 stm8s005k6 stm8s005c6 electrical characteristics
unit max (1) t yp conditions parameter symbol 1.3 hsi rc osc. (16 mhz) f cpu = f master /128 = 125 khz 0.7 hsi rc osc. (16 mhz/8) (2) f cpu = f master /128 = 15.625 khz 0.5 lsi rc osc. (128 khz) f cpu = f master = 128 khz (1) data based on characterization results, not tested in production. (2) default clock configuration measured with all peripherals of f. t otal current consumption in active halt mode 9.3.2.3 t able 23: t otal current consumption in active halt mode at v dd = 5 v unit max at 85 c (1) t yp conditions parameter symbol clock source flash mode (3) main voltage regulator (mvr) (2) a 1080 hse crystal osc. operating mode on supply current in i dd(ah) active halt mode (16 mhz) 320 200 lsi rc osc. (128 khz) 1030 hse crystal osc. power-down mode (16 mhz) 270 140 lsi rc osc. (128 khz) 59 / 103 docid022186 rev 3 electrical characteristics stm8s005k6 stm8s005c6
unit max at 85 c (1) t yp conditions parameter symbol clock source flash mode (3) main voltage regulator (mvr) (2) 120 68 lsi rc osc. (128 khz) operating mode of f 60 12 power-down mode (1) data based on characterization results, not tested in production. (2) configured by the regah bit in the clk_ickr register . (3) configured by the ahal t bit in the flash_cr1 register . t able 24: t otal current consumption in active halt mode at v dd = 3.3 v unit max at 85 c (1) t yp conditions parameter symbol clock source flash mode (3) main voltage regulator (mvr) (2) a 680 hse crystal osc. (16 mhz) operating mode on supply current in active halt mode i dd(ah) 320 200 lsi rc osc. (128 khz) 630 hse crystal osc. (16 mhz) power-down mode 270 140 lsi rc osc. (128 khz) 120 66 lsi rc osc. (128 khz) operating mode of f 60 10 power-down mode docid022186 rev 3 60 / 103 stm8s005k6 stm8s005c6 electrical characteristics
(1) data based on characterization results, not tested in production. (2) configured by the regah bit in the clk_ickr register . (3) configured by the ahal t bit in the flash_cr1 register . t otal current consumption in halt mode 9.3.2.4 t able 25: t otal current consumption in halt mode at v dd = 5 v unit max at 85 c (1) t yp conditions parameter symbol a 90 62 flash in operating mode, hsi clock after wakeup supply current in halt mode i dd(h) 25 6.5 flash in powerdown mode, hsi clock after wakeup (1) data based on characterization results, not tested in production. t able 26: t otal current consumption in halt mode at v dd = 3.3 v unit max at 85 c (1) t yp conditions parameter symbol a 90 60 flash in operating mode, hsi clock after wakeup supply current in halt mode i dd(h) 20 4.5 flash in powerdown mode, hsi clock after wakeup (1) data based on characterization results, not tested in production. low power mode wakeup times 9.3.2.5 t able 27: w akeup times unit max (1) t yp conditions parameter symbol s see note (2) 0 to 16 mhz w akeup time from wait mode to run t wu(wfi) 0.56 f cpu = f master = 16 mhz mode (3) 61 / 103 docid022186 rev 3 electrical characteristics stm8s005k6 stm8s005c6
unit max (1) t yp conditions parameter symbol 2 (6) 1 (6) hsi (after flash in operating mode (5) mvr voltage regulator on (4) w akeup time active halt mode to run mode (3) t wu(ah) wakeup) 3 (6) hsi (after flash in power-down mvr voltage regulator w akeup time active halt mode to run wakeup) mode (5) on (4) mode (3) 48 (6) hsi (after flash in operating mode (5) mvr voltage regulator of f (4) w akeup time active halt mode to run mode (3) wakeup) 50 (6) hsi (after flash in power-down mvr voltage regulator w akeup time active halt mode to run wakeup) mode (5) of f (4) mode (3) 52 flash in operating mode (5) w akeup time from halt mode to run t wu(h) 54 flash in power-down mode (5) mode (3) (1) data guaranteed by design, not tested in production. (2) t wu(wfi) = 2 x 1/f master + x 1/f cpu. (3) measured from interrupt event to interrupt vector fetch. (4) configured by the regah bit in the clk_ickr register . (5) configured by the ahal t bit in the flash_cr1 register . (6) plus 1 lsi clock depending on synchronization. t otal current consumption and timing in forced reset state 9.3.2.6 t able 28: t otal current consumption and timing in forced reset state unit max (1) t yp conditions parameter symbol a 500 v dd = 5 v supply current in reset state (2) i dd(r) 400 v dd = 3.3 v docid022186 rev 3 62 / 103 stm8s005k6 stm8s005c6 electrical characteristics
unit max (1) t yp conditions parameter symbol s 150 reset pin release to vector fetch t resetbl (1) data guaranteed by design, not tested in production. (2) characterized with all i/os tied to v ss . current consumption of on-chip peripherals 9.3.2.7 subject to general operating conditions for v dd and t a . hsi internal rc/f cpu = f master = 16 mhz. t able 29: peripheral current consumption unit t yp. parameter symbol a 230 tim1 supply current (1) i dd(tim1) 1 15 tim2 supply current (1) i dd(tim2) 90 tim3 timer supply current (1) i dd(tim3) 30 tim4 timer supply current (1) i dd(tim4) 1 10 uar t2 supply current (2) i dd(uar t2) 45 spi supply current (2) i dd(spi) 65 i 2 c supply current (2) i dd(i 2 c) 955 adc1 supply current when converting (3) i dd(adc1) (1) data based on a dif ferential i dd measurement between reset configuration and timer counter running at 16 mhz. no ic/oc programmed (no i/o pads toggling). not tested in production. (2) data based on a dif ferential i dd measurement between the on-chip peripheral when kept under reset and not clocked and the on-chip peripheral when clocked and not kept under reset. no i/o pads toggling. not tested in production. (3) data based on a dif ferential i dd measurement between reset configuration and continuous a/d conversions. not tested in production. 63 / 103 docid022186 rev 3 electrical characteristics stm8s005k6 stm8s005c6
current consumption curves 9.3.2.8 the following figures show typical current consumption measured with code executing in ram. figure 1 1: t yp. i dd(run) vs. v dd , hse user external clock, f cpu = 16 mhz figure 12: t yp. i dd(run) vs. f cpu , hse user external clock, v dd = 5 v docid022186 rev 3 64 / 103 stm8s005k6 stm8s005c6 electrical characteristics iid10236 0 0 . 5 1 1 . 5 2 2 . 5 3 3 . 5 4 4 . 5 5 0 5 1 0 1 5 2 0 2 5 3 0 i dd ( r un ) h s e [ m a ] f c p u [ m h z ] - 4 0 c 2 5 c 8 5 c iid10235 2 . 5 2 . 5 5 2 . 6 2 . 6 5 2 . 7 2 . 7 5 2 . 8 2 . 8 5 2 . 9 2 . 9 5 3 2 . 5 3 3 . 5 4 4 . 5 5 5 . 5 6 i dd ( r un ) h s e [ m a ] v dd [ v ] - 4 0 c 2 5 c 8 5 c
figure 13: t yp. i dd(run) vs. v dd , hsi rc osc, f cpu = 16 mhz figure 14: t yp. i dd(wfi) vs. v dd , hse user external clock, f cpu = 16 mhz figure 15: t yp. i dd(wfi) vs. f cpu , hse user external clock v dd = 5 v 65 / 103 docid022186 rev 3 electrical characteristics stm8s005k6 stm8s005c6 iid10238 1 1 . 2 1 . 4 1 . 6 1 . 8 2 2 . 2 2 . 4 2 . 5 3 3 . 5 4 4 . 5 5 5 . 5 6 i dd ( w f i ) h s e [ m a ] v dd [ v ] - 4 0 c 2 5 c 8 5 c iid10237 2 2 . 1 2 . 2 2 . 3 2 . 4 2 . 5 2 . 6 2 . 7 2 . 8 2 . 9 3 2 . 5 3 3 . 5 4 4 . 5 5 5 . 5 6 i dd ( r un ) h s i [ m a ] v dd [ v ] - 4 0 c 2 5 c 8 5 c iid10239 0 0 . 5 1 1 . 5 2 2 . 5 3 0 5 1 0 1 5 2 0 2 5 3 0 i dd ( w f i ) h s e [ m a ] f c p u [ m h z ] - 4 0 c 2 5 c 8 5 c
figure 16: t yp. i dd(wfi) vs. v dd , hsi rc osc, f cpu = 16 mhz external clock sources and timing characteristics 9.3.3 hse user external clock subject to general operating conditions for v dd and t a . t able 30: hse user external clock characteristics unit max min conditions parameter symbol mhz 16 0 user external clock source frequency f hse_ext v v dd + 0.3 v 0.7 x v dd oscin input pin high level voltage v hseh (1) 0.3 x v dd v ss oscin input pin low level voltage v hsel (1) a +1 -1 v ss < v in < v dd oscin input leakage current i leak_hse (1) data based on characterization results, not tested in production. docid022186 rev 3 66 / 103 stm8s005k6 stm8s005c6 electrical characteristics iid10240 1 1 . 1 1 . 2 1 . 3 1 . 4 1 . 5 1 . 6 1 . 7 1 . 8 1 . 9 2 2 . 5 3 3 . 5 4 4 . 5 5 5 . 5 6 i dd ( w f i ) h s i [ m a ] v dd [ v ] - 4 0 c 2 5 c 8 5 c
figure 17: hse external clocksource hse crystal/ceramic resonator oscillator the hse clock can be supplied with a 1 to 16 mhz crystal/ceramic resonator oscillator . all the information given in this paragraph is based on characterization results with specified typical external components. in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. refer to the crystal resonator manufacturer for more details (frequency , package, accuracy ...). t able 31: hse oscillator characteristics unit max t yp min conditions parameter symbol mhz 16 1 external high speed oscillator frequency f hse k? 220 feedback resistor r f pf 20 recommended load capacitance (2) c (1) ma 6 (startup) c = 20 pf , hse oscillator power consumption i dd(hse) 1.6 (stabilized) (3) f osc = 16 mhz 6 (startup) c = 10 pf , 1.2 (stabilized) (3) f osc =16 mhz ma/v 5 oscillator transconductance g m ms 1 v dd is stabilized startup time t su(hse) (4) (1) c is approximately equivalent to 2 x crystal cload. 67 / 103 docid022186 rev 3 electrical characteristics stm8s005k6 stm8s005c6 v hseh v hsel exter nal cloc k source oscin f hse stm8
(2) the oscillator selection can be optimized in terms of supply current using a high quality resonator with small r m value. refer to crystal manufacturer for more details (3) data based on characterization results, not tested in production. (4) t su(hse) is the start-up time measured from the moment it is enabled (by software) to a stabilized 16 mhz oscillation is reached. this value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer . figure 18: hse oscillator circuit diagram hse oscillator critical g m equation g mcrit = (2 f hse ) 2 r m (2co + c) 2 r m : notional resistance (see crystal specification) l m : notional inductance (see crystal specification) c m : notional capacitance (see crystal specification) co: shunt capacitance (see crystal specification) c l1 = c l2 = c: grounded external capacitance g m >> g mcrit internal clock sources and timing characteristics 9.3.4 subject to general operating conditions for v dd and t a . high speed internal rc oscillator (hsi) t able 32: hsi oscillator characteristics unit max t yp min conditions parameter symbol mhz 16 frequency f hsi docid022186 rev 3 68 / 103 stm8s005k6 stm8s005c6 electrical characteristics oscout oscin f hse to core c l1 c l2 r f stm8 resonator consumption control g m r m c m l m c o resonator
unit max t yp min conditions parameter symbol % 1.0 (2) user-trimmed with clk_hsitrimr register accuracy of hsi oscillator acc hsi for given v dd and t a conditions (1) 5.0 v dd = 5 v , t a = 25c (3) accuracy of hsi oscillator (factory calibrated) 5.0 -5.0 v dd = 5 v , -40 c t a 85 c s 1.0 (2) hsi oscillator wakeup time including calibration t su(hsi) a 250 (3) 170 hsi oscillator power consumption i dd(hsi) (1) refer to application note. (2) guaranteed by design, not tested in production. (3) data based on characterization results, not tested in production. figure 19: t ypical hsi frequency variation vs v dd @ 3 temperatures low speed internal rc oscillator (lsi) subject to general operating conditions for v dd and t a . 69 / 103 docid022186 rev 3 electrical characteristics stm8s005k6 stm8s005c6 iid10241 15 . 5 15 . 6 15 . 7 15 . 8 15 . 9 1 6 16 . 1 16 . 2 16 . 3 16 . 4 16 . 5 2 . 5 3 3 . 5 4 4 . 5 5 5 . 5 6 h s i f r equen cy [ m h z ] v dd [ v ] - 4 0 c 2 5 c 8 5 c
t able 33: lsi oscillator characteristics unit max t yp min parameter symbol khz 128 frequency f lsi s 7 (1) lsi oscillator wakeup time t su(lsi) a 5 lsi oscillator power consumption i dd(lsi) (1) guaranteeed by design, not tested in production. figure 20: t ypical lsi frequency variation vs v dd @ 3 temperatures memory characteristics 9.3.5 ram and hardware registers t able 34: ram and hardware registers unit min conditions parameter symbol v v it-max (2) halt mode (or reset) data retention mode (1) v rm (1) minimum supply voltage without losing data stored in ram (in halt mode or under reset) or in hardware registers (only in halt mode). guaranteed by design, not tested in production. refer to operating conditions for the value of v it-max (2) refer to the operating conditions section for the value of v it-max flash program memory/data eeprom memory general conditions: t a = -40 to 85c. docid022186 rev 3 70 / 103 stm8s005k6 stm8s005c6 electrical characteristics iid10242 10 0 10 5 11 0 11 5 12 0 12 5 13 0 13 5 14 0 14 5 15 0 2 . 5 3 3 . 5 4 4 . 5 5 5 . 5 6 l s i f r equen cy [ m h z ] v dd [ v ] - 4 0 c 2 5 c 8 5 c
t able 35: flash program memory/data eeprom memory unit max t yp min (1) conditions parameter symbol v 5.5 2.95 f cpu 16 mhz operating voltage (all modes, execution/write/erase) v dd ms 6.6 6.0 standard programming time (including erase) for t prog byte/word/block (1 byte/4 bytes/128 bytes) ms 3.3 3.0 fast programming time for 1 block (128 bytes) ms 3.3 3.0 erase time for 1 block (128 bytes) t erase cycles 100 t a = 85 c erase/write cycles (2) (program memory) n r w 100 k t a = 85 c erase/write cycles(data memory) (2) years 20 t ret = 55 c data retention (program memory) after 100 erase/write cycles at t a = 85 c t ret 20 data retention (data memory) after 10 k erase/write cycles at t a = 85 c 1 t ret = 85 c data retention (data memory) after 100 k erase/write cyclesat t a = 85 c ma 2.0 supply current (flash programming or erasing for 1 to 128 bytes) i dd (1) data based on characterization results, not tested in production. (2) the physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a write/erase operation addresses a single byte. 71 / 103 docid022186 rev 3 electrical characteristics stm8s005k6 stm8s005c6
i/o port pin characteristics 9.3.6 general characteristics subject to general operating conditions for v dd and t a unless otherwise specified. all unused pins must be kept at a fixed voltage: using the output mode of the i/o for example or an external pull-up or pull-down resistor . t able 36: i/o static characteristics unit max t yp min conditions parameter symbol v 0.3 x v dd -0.3 v dd = 5 v input low level voltage v il v v dd + 0.3 v 0.7 x v dd input high level voltage v ih mv 700 hysteresis (1) v hys k 80 55 30 v dd = 5 v , v in = v ss pull-up resistor r pu ns 35 (3) fast i/os load = 50 pf rise and fall time(10 % - 90 %) t r , t f ns 125 (3) standard and high sink i/osload = 50 pf a 1.0 (2) v ss v in v dd input leakage current, analog and digital i lkg na 250 (2) v ss v in v dd analog input leakage current i lkg ana a 1.0 (2) injection current 4 ma leakage current in adjacent i/o (2) i lkg(inj) (1) hysteresis voltage between schmitt trigger switching levels. based on characterization results, not tested in production. (2) data based on characterization results, not tested in production. (3) data guaranteed by design, not tested in production. docid022186 rev 3 72 / 103 stm8s005k6 stm8s005c6 electrical characteristics
figure 21: t ypical v il and v ih vs v dd @ 3 temperatures figure 22: t ypical pull-up resistance vs v dd @ 3 temperatures figure 23: t ypical pull-up current vs v dd @ 3 temperatures 1. the pull-up is a pure resistor (slope goes through 0). 73 / 103 docid022186 rev 3 electrical characteristics stm8s005k6 stm8s005c6 iid10245 0 2 0 4 0 6 0 8 0 10 0 12 0 14 0 0 1 2 3 4 5 6 p u l l - u p c u rr en t [ a ] v dd [ v ] - 4 0 c 2 5 c 8 5 c iid10243 0 1 2 3 4 5 6 2 . 5 3 3 . 5 4 4 . 5 5 5 . 5 6 v i l / v i h [ v ] v dd [ v ] - 4 0 c 2 5 c 8 5 c iid10244 3 0 3 5 4 0 4 5 5 0 5 5 6 0 2 . 5 3 3 . 5 4 4 . 5 5 5 . 5 6 p u l l - u p r e s i s t an c e [ k w ] v dd [ v ] - 4 0 c 2 5 c 8 5 c
t able 37: output driving current (standard ports) unit max min conditions parameter symbol v 1.0 (1) i io = 4 ma, v dd = 3.3 v output low level with four pins sunk v ol 2.0 i io = 10 ma, v dd = 5 v output low level with eight pins sunk v 2.0 (1) i io = 4 ma, v dd = 3.3 v output high level with four pins sourced v oh 2.4 i io = 10 ma, v dd = 5 v output high level with eight pins sourced (1) data based on characterization results, not tested in production t able 38: output driving current (true open drain ports) unit max conditions parameter symbol v 1.5 (1) i io = 10 ma, v dd = 3.3 v output low level with two pins sunk v ol 1.0 i io = 10 ma, v dd = 5 v 2.0 (1) i io = 20 ma, v dd = 5 v (1) data based on characterization results, not tested in production t able 39: output driving current (high sink ports) unit max min conditions parameter symbol v 1.1 (1) i io = 10 ma, v dd = 3.3 v output low level with four pins sunk v ol 0.9 i io = 10 ma, v dd = 5 v output low level with eight pins sunk docid022186 rev 3 74 / 103 stm8s005k6 stm8s005c6 electrical characteristics
unit max min conditions parameter symbol 1.6 (1) i io = 20 ma, v dd = 5 v output low level with four pins sunk 1.9 (1) i io = 10 ma, v dd = 3.3 v output high level with four pins sourced v oh 3.8 i io = 10 ma, v dd = 5 v output high level with eight pins sourced 2.9 (1) i io = 20 ma, v dd = 5 v output high level with four pins sourced (1) data based on characterization results, not tested in production t ypical output level curves 9.3.7 the following figures show typical output level curves measured with output on a single pin. figure 24: t yp. v ol @ v dd = 5 v (standard ports) 75 / 103 docid022186 rev 3 electrical characteristics stm8s005k6 stm8s005c6 iid10224 0 0 . 2 5 0 . 5 0 . 7 5 1 1 . 2 5 1 . 5 0 2 4 6 8 1 0 1 2 v o l [ v ] i o l [ m a ] - 4 0 c 2 5 c 8 5 c
figure 25: t yp. v ol @ v dd = 3.3 v (standard ports) figure 26: t yp. v ol @ v dd = 5 v (true open drain ports) figure 27: t yp. v ol @ v dd = 3.3 v (true open drain ports) docid022186 rev 3 76 / 103 stm8s005k6 stm8s005c6 electrical characteristics iid10225 0 0 . 2 5 0 . 5 0 . 7 5 1 1 . 2 5 1 . 5 0 1 2 3 4 5 6 7 v o l [ v ] i o l [ m a ] - 4 0 c 2 5 c 8 5 c iid10227 0 0 . 2 5 0 . 5 0 . 7 5 1 1 . 2 5 1 . 5 1 . 7 5 2 0 2 4 6 8 1 0 1 2 1 4 v o l [ v ] i o l [ m a ] - 4 0 c 2 5 c 8 5 c iid10226 0 0 . 2 5 0 . 5 0 . 7 5 1 1 . 2 5 1 . 5 1 . 7 5 2 0 5 1 0 1 5 2 0 2 5 v o l [ v ] i o l [ m a ] - 4 0 c 2 5 c 8 5 c
figure 28: t yp. v ol @ v dd = 5 v (high sink ports) figure 29: t yp. v ol @ v dd = 3.3 v (high sink ports) figure 30: t yp. v dd - v oh @ v dd = 5 v (standard ports) 77 / 103 docid022186 rev 3 electrical characteristics stm8s005k6 stm8s005c6 iid10228 0 0 . 2 5 0 . 5 0 . 7 5 1 1 . 2 5 1 . 5 0 5 1 0 1 5 2 0 2 5 v o l [ v ] i o l [ m a ] - 4 0 c 2 5 c 8 5 c iid10229 0 0 . 2 5 0 . 5 0 . 7 5 1 1 . 2 5 1 . 5 0 2 4 6 8 1 0 1 2 1 4 v o l [ v ] i o l [ m a ] - 4 0 c 2 5 c 8 5 c iid10230 0 0 . 2 5 0 . 5 0 . 7 5 1 1 . 2 5 1 . 5 1 . 7 5 2 0 2 4 6 8 1 0 1 2 v d d - v o h [ v ] i o h [ m a ] - 4 0 c 2 5 c 8 5 c
figure 31: t yp. v dd - v oh @ v dd = 3.3 v (standard ports) figure 32: t yp. v dd - v oh @ v dd = 5 v (high sink ports) figure 33: t yp. v dd - v oh @ v dd = 3.3 v (high sink ports) docid022186 rev 3 78 / 103 stm8s005k6 stm8s005c6 electrical characteristics iid10231 0 0 . 2 5 0 . 5 0 . 7 5 1 1 . 2 5 1 . 5 1 . 7 5 2 0 1 2 3 4 5 6 7 v d d - v o h [ v ] i o h [ m a ] - 4 0 c 2 5 c 8 5 c iid10232 0 0 . 2 5 0 . 5 0 . 7 5 1 1 . 2 5 1 . 5 1 . 7 5 2 0 5 1 0 1 5 2 0 2 5 v d d - v o h [ v ] i o h [ m a ] - 4 0 c 2 5 c 8 5 c iid10233 0 0 . 2 5 0 . 5 0 . 7 5 1 1 . 2 5 1 . 5 1 . 7 5 2 0 2 4 6 8 1 0 1 2 1 4 v d d - v o h [ v ] i o h [ m a ] - 4 0 c 2 5 c 8 5 c
reset pin characteristics 9.3.8 subject to general operating conditions for v dd and t a unless otherwise specified. t able 40: nrst pin characteristics unit max t yp min conditions parameter symbol v 0.3 x v dd -0.3 nrst input low v il(nrst) level voltage (1) v dd + 0.3 0.7 x v dd i ol =2 ma nrst input high v ih(nrst) level voltage (1) 0.5 nrst output low v ol(nrst) level voltage (1) k 80 55 30 nrst pull-up r pu(nrst) resistor (2) ns 75 nrst input filtered t i fp(nrst) pulse (3) 500 nrst input not t in fp(nrst) filtered pulse (3) s 15 nrst output pulse (3) t op(nrst) (1) data based on characterization results, not tested in production. (2) the r pu pull-up equivalent resistor is based on a resistive transistor (3) data guaranteed by design, not tested in production. 79 / 103 docid022186 rev 3 electrical characteristics stm8s005k6 stm8s005c6
figure 34: t ypical nrst v il and v ih vs v dd @ 3 temperatures figure 35: t ypical nrst pull-up resistance vs v dd @ 3 temperatures figure 36: t ypical nrst pull-up current vs v dd @ 3 temperatures docid022186 rev 3 80 / 103 stm8s005k6 stm8s005c6 electrical characteristics iid10248 0 0 . 5 1 1 . 5 2 2 . 5 3 3 . 5 4 4 . 5 5 5 . 5 6 2 . 5 3 3 . 5 4 4 . 5 5 5 . 5 6 v i l / v i h [ v ] v dd [ v ] - 4 0 c 2 5 c 8 5 c iid10246 0 2 0 4 0 6 0 8 0 10 0 12 0 14 0 2 2 . 5 3 3 . 5 4 4 . 5 5 5 . 5 6 nr ese t p u l l - u p c u rr en t [ a ] v dd [ v ] - 4 0 c 2 5 c 8 5 c iid10234 3 0 3 5 4 0 4 5 5 0 5 5 6 0 2 . 5 3 3 . 5 4 4 . 5 5 5 . 5 6 nr ese t p u l l - u p r e s i s t an c e [ k w ] v dd [ v ] - 4 0 c 2 5 c 8 5 c
the reset network shown in the following figure protects the device against parasitic resets. the user must ensure that the level on the nrst pin can go below v il(nrst) max. (see t able 40: nrst pin characteristics ), otherwise the reset is not taken into account internally . for power consumption sensitive applications, the external reset capacitor value can be reduced to limit the charge/discharge current. if nrst signal is used to reset external circuitry , attention must be taken to the charge/discharge time of the external capacitor to fulfill the external devices reset timing conditions. minimum recommended capacity is 100 nf . figure 37: recommended reset pin protection spi serial peripheral interface 9.3.9 unless otherwise specified, the parameters given in the following table are derived from tests performed under ambient temperature, f master frequency and v dd supply voltage conditions. t master = 1/f master . refer to i/o port characteristics for more details on the input/output alternate function characteristics (nss, sck, mosi, miso). t able 41: spi characteristics unit max min conditions parameter symbol mhz 8 0 master mode spi clock frequency f sck 1 t c(sck) 6 0 slave mode ns 25 capacitive load: c = 30 pf spi clock rise and fall time t r(sck) t f(sck) ns 4 x t master slave mode nss setup time t su(nss) (1) ns 70 slave mode nss hold time t h(nss) (1) 81 / 103 docid022186 rev 3 electrical characteristics stm8s005k6 stm8s005c6 exter nal reset circuit (optional) 0.1 f nrst vdd rpu filter inter nal reset stm8
unit max min conditions parameter symbol ns t sck /2 + 15 t sck /2 - 15 master mode sck high and low time t w(sckh) (1) t w(sckl) (1) ns 5 master mode data input setup time t su(mi) (1) t su(si) (1) ns 5 slave mode data input setup time ns 7 master mode data input hold time t h(mi) (1) t h(si) (1) ns 10 slave mode data input hold time ns 3 x t master slave mode data output access time t a(so) (1) (2) ns 25 slave mode data output disable time t dis(so) (1) (3) ns 73 slave mode (after enable edge) data output valid time t v(so) (1) ns 36 master mode (after enable edge) data output valid time t v(mo) (1) ns 28 slave mode (after enable edge) data output hold time t h(so) (1) ns 12 master mode (after enable edge) t h(mo) (1) (1) v alues based on design simulation and/or characterization results, and not tested in production. (2) min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. (3) min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in hi-z. docid022186 rev 3 82 / 103 stm8s005k6 stm8s005c6 electrical characteristics
figure 38: spi timing diagram - slave mode and cpha = 0 figure 39: spi timing diagram - slave mode and cpha = 1 (1) 1. measurement points are made at cmos levels: 0.3 v dd and 0.7 v dd . 83 / 103 docid022186 rev 3 electrical characteristics stm8s005k6 stm8s005c6 ai14135 sck input c p h a =1 m o s i i n p u t m i s o o u t p u t c p h a =1 m s b o u t m s b i n b i t 6 o u t l s b i n l s b o u t c p o l = 0 c p o l = 1 b i t 1 i n t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) nss input ai14134 sck input c p h a = 0 m o s i i n p u t m i s o o u t p u t c p h a = 0 m s b o u t m s b i n b i t 6 o u t l s b i n l s b o u t c p o l = 0 c p o l = 1 b i t 1 i n n s s input t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si)
figure 40: spi timing diagram - master mode (1) 1. measurement points are made at cmos levels: 0.3 v dd and 0.7 v dd . i 2 c interface characteristics 9.3.10 t able 42: i 2 c characteristics unit fast mode i 2 c (1) standard mode i 2 c parameter symbol max (2) min (2) max (2) min (2) s 1.3 4.7 scl clock low time t w(scll) s 0.6 4.0 scl clock high time t w(sclh) ns 100 250 sda setup time t su(sda) ns 900 (3) 0 (4) 0 (3) sda data hold time t h(sda) ns 300 1000 sda and scl rise time t r(sda) t r(scl) ns 300 300 sda and scl fall time t f(sda) t f(scl) docid022186 rev 3 84 / 103 stm8s005k6 stm8s005c6 electrical characteristics ai14136b sck intput c p h a = 0 m o s i out u t m i s o in p u t c p h a = 0 m s bin m s b out b i t 6 in l s b out l s b in c p o l = 0 c p o l = 1 b i t 1 out n s s input t c(sck) t w(sckh) t w(sckl) t r(sck) t f(sck) t h(mi) high sck output c p h a =1 c p h a =1 c p o l = 0 c p o l = 1 t su(mi) t v(mo) t h(mo)
unit fast mode i 2 c (1) standard mode i 2 c parameter symbol max (2) min (2) max (2) min (2) s 0.6 4.0 st ar t condition hold time t h(st a) s 0.6 4.7 repeated st ar t condition setup time t su(st a) s 0.6 4.0 st op condition setup time t su(st o) s 1.3 4.7 st op to st ar t condition time (bus free) t w(st o:st a) pf 400 400 capacitive load for each bus line c b (1) f master , must be at least 8 mhz to achieve max fast i 2 c speed (400khz). (2) data based on standard i 2 c protocol requirement, not tested in production. (3) the maximum hold time of the start condition has only to be met if the interface does not stretch the low time. (4) the device must internally provide a hold time of at least 300 ns for the sda signal in order to bridge the undefined region of the falling edge of scl. figure 41: t ypical application with i 2 c bus and timing diagram (1) 1. measurement points are made at cmos levels: 0.3 x v dd and 0.7 x v dd 85 / 103 docid022186 rev 3 electrical characteristics stm8s005k6 stm8s005c6 ai15385b s t a r t s d a i2c b us v dd v dd stm8sx05xx s d a scl t f(s d a) t r(s d a) scl t h(s t a) t w(sclh) t w(scll) t su(s d a) t r(scl) t f(scl) t h(s d a) s t a r t repe a ted s t a r t t su(s t a) t su(s t o) s t op t su(s t a:s t o)
10-bit adc characteristics 9.3.1 1 subject to general operating conditions for v dda , f master , and t a unless otherwise specified. t able 43: adc characteristics unit max t yp min conditions parameter symbol mhz 4.0 1.0 v dda =2.95 to 5.5 v adc clock frequency f adc 6.0 1.0 v dda =4.5 to 5.5 v v 5.5 3.0 analog supply v dda v v dda 2.75 (1) positive reference voltage v ref+ v 0.5 (1) v ssa negative reference voltage v ref- v v dda v ssa conversion voltage range (2) v ain v v ref+ v ref- devices with external v ref+ /v ref- pins pf 3.0 internal sample and hold capacitor c adc s 0.75 f adc = 4 mhz sampling time t s (2) 0.5 f adc = 6 mhz s 7.0 w akeup time from standby t st ab s 3.5 f adc = 4 mhz t otal conversion time (including sampling time, 10-bit resolution) t conv s 2.33 f adc = 6 mhz 1/f adc 14 (1) data guaranteed by design, not tested in production.. (2) during the sample time the input capacitance c ain (3 pf max) can be charged/discharged by the external source. the internal resistance of the analog source must allow the capacitance to reach its final voltage level within t s. after the end of the sample time t s , docid022186 rev 3 86 / 103 stm8s005k6 stm8s005c6 electrical characteristics
changes of the analog input voltage have no ef fect on the conversion result. v alues for the sample clock t s depend on programming. t able 44: adc accuracy with r ain < 10 k , v dda = 5 v unit max (1) t yp conditions parameter symbol lsb 2.5 1.0 f adc = 2 mhz t otal unadjusted error (2) |e t | 3.0 1.4 f adc = 4 mhz 3.5 1.6 f adc = 6 mhz 2.0 0.6 f adc = 2 mhz of fset error (2) |e o | 2.5 1.1 f adc = 4 mhz 2.5 1.2 f adc = 6 mhz 2.0 0.2 f adc = 2 mhz gain error (2) |e g | 2.5 0.6 f adc = 4 mhz 2.5 0.8 f adc = 6 mhz 1.5 0.7 f adc = 2 mhz dif ferential linearity error (2) |e d | 1.5 0.7 f adc = 4 mhz 1.5 0.8 f adc = 6 mhz 1.5 0.6 f adc = 2 mhz integral linearity error (2) |e l | 1.5 0.6 f adc = 4 mhz 1.5 0.6 f adc = 6 mhz (1) data based on characterisation results, not tested in production. (2) adc accuracy vs. negative injection current: injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. 87 / 103 docid022186 rev 3 electrical characteristics stm8s005k6 stm8s005c6
any positive injection current within the limits specified for i inj(pin) and i inj(pin) in the i/o port pin characteristics section does not af fect the adc accuracy . t able 45: adc accuracy with r ain < 10 k r ain , v dda = 3.3 v unit max (1) t yp conditions parameter symbol lsb 2.0 1.1 f adc = 2 mhz t otal unadjusted error (2) |e t | 2.5 1.6 f adc = 4 mhz 1.5 0.7 f adc = 2 mhz of fset error (2) |e o | 2.0 1.3 f adc = 4 mhz 1.5 0.2 f adc = 2 mhz gain error (2) |e g | 2.0 0.5 f adc = 4 mhz 1.0 0.7 f adc = 2 mhz dif ferential linearity error (2) |e d | 1.0 0.7 f adc = 4 mhz 1.5 0.6 f adc = 2 mhz integral linearity error (2) |e l | 1.5 0.6 f adc = 4 mhz (1) data based on characterisation results, not tested in production. (2) adc accuracy vs. negative injection current: injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. any positive injection current within the limits specified for i inj(pin) and i inj(pin) in i/o port pin characteristics does not af fect the adc accuracy . docid022186 rev 3 88 / 103 stm8s005k6 stm8s005c6 electrical characteristics
figure 42: adc accuracy characteristics 1. example of an actual transfer curve. 2. the ideal transfer curve 3. end point correlation line e t = t otal unadjusted error: maximum deviation between the actual and the ideal transfer curves. e o = of fset error: deviation between the first actual transition and the first ideal one. e g = gain error: deviation between the last ideal transition and the last actual one. e d = dif ferential linearity error: maximum deviation between actual steps and the ideal one. e l = integral linearity error: maximum deviation between any actual transition and the end point correlation line. figure 43: t ypical application with adc emc characteristics 9.3.12 susceptibility tests are performed on a sample basis during product characterization. 89 / 103 docid022186 rev 3 electrical characteristics stm8s005k6 stm8s005c6 stm8 10-bit a/d con v ersion r ain c ain v ain ainx v dd v t 0.6 v v t 0.6 v i l 1 a c adc
functional ems (electromagnetic susceptibility) 9.3.12.1 while executing a simple application (toggling 2 leds through i/o ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the leds). ? fesd: functional electrostatic discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. this test conforms with the iec 61000-4-2 standard. ? ftb: a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100 pf capacitor , until a functional disturbance occurs. this test conforms with the iec 61000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in the table below based on the ems levels and classes defined in application note an1709 (emc design guide for stmicrocontrollers). designing hardened software to avoid noise problems 9.3.12.2 emc characterization and optimization are performed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular . therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. software recommendations the software flowchart must include the management of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers...) prequalification trials most of the common failures (unexpected reset and program counter corruption) can be recovered by applying a low state on the nrst pin or the oscillator pins for 1 second. t o complete these trials, esd stress can be applied directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring. see application note an1015 (software techniques for improving microcontroller emc performance). t able 46: ems data level/ class conditions parameter symbol 2/b (1) v dd = 5 v , t a = 25 c, f master = 16 mhz, conforming to iec 1000-4-2 v oltage limits to be applied on any i/o pin to induce a functional disturbance v fesd 4/a (1) v dd = 5 v , t a = 25 c ,f master = 16 mhz,conforming to iec 1000-4-4 fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v eftb docid022186 rev 3 90 / 103 stm8s005k6 stm8s005c6 electrical characteristics
(1) data obtained with hsi clock configuration, after applying hw recommendations described in an2860 (emc guidelines for stm8s microcontrollers). electromagnetic interference (emi) 9.3.12.3 emission tests conform to the iec61967-2 standard for test software, board layout and pin loading. t able 47: emi data unit conditions parameter symbol max f hse /f cpu (1) monitored frequency band general conditions 8 mhz/ 16 mhz 8 mhz/ 8 mhz dbv 14 13 0.1 mhz to 30 mhz v dd = 5 v , t a = +25 c, peak level s emi 19 23 30 mhz to 130 mhz lqfp48 package conforming to iec61967-2 -4.0 -4.0 130 mhz to 1 ghz 1.5 2.0 sae emi level (1) data based on characterization results, not tested in production. absolute maximum ratings (electrical sensitivity) 9.3.12.4 based on two dif ferent tests (esd and lu) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity . for more details, refer to the application note an1 181. electrostatic discharge (esd) 9.3.12.5 electrostatic discharges (3 positive then 3 negative pulses separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). this test conforms to the jesd22-a1 14a/a1 15a standard. for more details, refer to the application note an1 181. 91 / 103 docid022186 rev 3 electrical characteristics stm8s005k6 stm8s005c6
t able 48: esd absolute maximum ratings unit maximum value (1) class conditions ratings symbol v 2000 a t a = +25c, conforming to jesd22-a1 14 electrostatic discharge voltage (human body model) v esd(hbm) v 1000 iv t a =+25c, conforming to jesd22-c101 electrostatic discharge voltage (charge device model) v esd(cdm) (1) data based on characterization results, not tested in production static latch-up 9.3.12.6 t wo complementary static tests are required on 10 parts to assess the latch-up performance: ? a supply overvoltage (applied to each power supply pin) ? a current injection (applied to each input, output and configurable i/o pin) are performed on each sample. this test conforms to the eia/jesd 78 ic latch-up standard. for more details, refer to the application note an1 181. t able 49: electrical sensitivities class (1) conditions parameter symbol a t a = +25 c static latch-up class lu a t a = +85 c (1) class description: a class is an stmicroelectronics internal specification. all its limits are higher than the jedec specifications, that means when a device belongs to class a it exceeds the jedec standard. b class strictly covers all the jedec criteria (international standard). docid022186 rev 3 92 / 103 stm8s005k6 stm8s005c6 electrical characteristics
package information 10 in order to meet environmental requirements, st of fers these devices in dif ferent grades of ecop ack ? packages, depending on their level of environmental compliance. ecop ack ? specifications, grade definitions and product status are available at: www .st.com. ecop ack ? is an st trademark. 48-pin lqfp package mechanical data 10.1 figure 44: 48-pin low profile quad flat package (7 x 7) t able 50: 48-pin low profile quad flat package mechanical data inches (1) mm dim. max t yp min max t yp min 0.0630 1.600 a 0.0059 0.0020 0.150 0.050 a1 0.0571 0.0551 0.0531 1.450 1.400 1.350 a2 0.0106 0.0087 0.0067 0.270 0.220 0.170 b 0.0079 0.0035 0.200 0.090 c 0.3622 0.3543 0.3465 9.200 9.000 8.800 d 93 / 103 docid022186 rev 3 package information stm8s005k6 stm8s005c6 5b_me l a1 k l1 c a a2 ccc c d d1 d3 e3 e1 e 24 25 36 37 b 48 1 pin 1 identification 12 13
inches (1) mm dim. max t yp min max t yp min 0.2835 0.2756 0.2677 7.200 7.000 6.800 d1 0.2165 5.500 d3 0.3622 0.3543 0.3465 9.200 9.000 8.800 e 0.2835 0.2756 0.2677 7.200 7.000 6.800 e1 0.2165 5.500 e3 0.0197 0.500 e 0.0295 0.0236 0.0177 0.750 0.600 0.450 l 0.0394 1.000 l1 7.0 3.5 0 7.0 3.5 0 k 0.0031 0.080 ccc (1) v alues in inches are converted from mm and rounded to 4 decimal digits docid022186 rev 3 94 / 103 stm8s005k6 stm8s005c6 package information
32-pin lqfp package mechanical data 10.2 figure 45: 32-pin low profile quad flat package (7 x 7) t able 51: 32-pin low profile quad flat package mechanical data inches (1) mm dim. max t yp min max t yp min 0.0630 1.600 a 0.0059 0.0020 0.150 0.050 a1 0.0571 0.0551 0.0531 1.450 1.400 1.350 a2 0.0177 0.0146 0.01 18 0.450 0.370 0.300 b 0.0079 0.0035 0.200 0.090 c 0.3622 0.3543 0.3465 9.200 9.000 8.800 d 0.2835 0.2756 0.2677 7.200 7.000 6.800 d1 0.2205 5.600 d3 0.3622 0.3543 0.3465 9.200 9.000 8.800 e 0.2835 0.2756 0.2677 7.200 7.000 6.800 e1 95 / 103 docid022186 rev 3 package information stm8s005k6 stm8s005c6 5v_me l a1 k l1 c a a2 ccc c d d1 d3 e3 e1 e 16 17 24 25 b 32 1 pin 1 identification 8 9
inches (1) mm dim. max t yp min max t yp min 0.2205 5.600 e3 0.0315 0.800 e 0.0295 0.0236 0.0177 0.750 0.600 0.450 l 0.0394 1.000 l1 7.0 3.5 0 7.0 3.5 0 k 0.0039 0.100 ccc (1) v alues in inches are converted from mm and rounded to 4 decimal digits docid022186 rev 3 96 / 103 stm8s005k6 stm8s005c6 package information
thermal characteristics 1 1 the maximum chip junction temperature (t j max ) must never exceed the values given in operating conditions the maximum chip-junction temperature, t jmax , in degrees celsius, may be calculated using the following equation: t jmax = t amax + (p dmax x ja ) where: ? t amax is the maximum ambient temperature in c ? ja is the package junction-to-ambient thermal resistance in c/w ? p dmax is the sum of p intmax and p i/omax (p dmax = p intmax + p i/omax ) ? p intmax is the product of i dd andv dd , expressed in w atts. this is the maximum chip internal power . ? p i/omax represents the maximum power dissipation on output pinswhere:p i/omax = (v ol *i ol ) + ((v dd -v oh) *i oh ), taking into account the actual v ol /i ol and v oh /i oh of the i/os at low and high level in the application. t able 52: thermal characteristics (1) unit v alue parameter symbol c/w 57 thermal resistance junction-ambient lqfp 48 - 7 x 7 mm ja c/w 60 thermal resistance junction-ambient lqfp 32 - 7 x 7 mm ja 1. thermal resistances are based on jedec jesd51-2 with 4-layer pcb in a natural convection environment. reference document 1 1.1 jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). a vailable from www .jedec.org. selecting the product temperature range 1 1.2 when ordering the microcontroller , the temperature range is specified in the order code. the following example shows how to calculate the temperature range needed for a given application. assuming the following application conditions: ? maximum ambient temperature t amaz = 82 c (measured according to jesd51-2) ? i ddmax = 15 ma, v dd = 5.5 v 97 / 103 docid022186 rev 3 thermal characteristics stm8s005k6 stm8s005c6
? maximum 8 standard i/os used at the same time in output at low level with i ol = 10 ma, v ol = 2 v ? maximum 4 high sink i/os used at the same time in output at low level with i ol = 20 ma, v ol = 1.5 v ? maximum 2 true open drain i/os used at the same time in output at low level with i ol = 20 ma, v ol = 2 v p intmax = 15 ma x 5.5 v = 82.5 mw p iomax = (10 ma x 2 v x 8 )+(20 ma x 2 v x 2)+(20 ma x 1.5 v x 4) = 360 mw this gives: p intmax = 82.5 mw and p iomax 360 mw : p dmax = 82.5 mw + 360 mw thus: p dmax = 443 mw t jmax for lqfp32 can be calculated as follows, using the thermal resistance ja : t jmax = 75 c + (59 c/w x 464 mw) = 75c + 27c = 102 c this is within the range of the suf fix 6 version parts (-40 < t j < 106 c). in this case, parts must be ordered at least with the temperature range suf fix 6. docid022186 rev 3 98 / 103 stm8s005k6 stm8s005c6 thermal characteristics
ordering information 12 figure 46: stm8s005xx value line ordering information scheme 1. for a list of available options (e.g. memory size, package) and orderable part numbers or for further information on any aspect of this device, please go to www .st.com or contact the st sales of fice nearest to you. 99 / 103 docid022186 rev 3 ordering information stm8s005k6 stm8s005c6 product class pin count k = 32 pins c = 48 pins p ac kage type t = lqfp example: sub-f amily type 005 = v alue line stm8s005x f amily type s = standard t emper ature r ange 6 = -40 c to 85 c prog r am memor y siz e 6 = 32 kb ytes p ac kage pitch no char acter = 0.5 mm c = 0.8 mm p ac king no char acter = t r a y or tube tr = t ape and reel stm8 s 005 k 6 t 6 c tr
stm8 development tools 13 development tools for the stm8 microcontrollers include the full-featured st ice emulation system supported by a complete software tool package including c compiler , assembler and integrated development environment with high-level language debugger . in addition, the stm8 is to be supported by a complete range of tools including starter kits, evaluation boards and a low-cost in-circuit debugger/programmer . emulation and in-circuit debugging tools 13.1 the st ice emulation system of fers a complete range of emulation and in-circuit debugging features on a platform that is designed for versatility and cost-ef fectiveness. in addition, stm8 application development is supported by a low-cost in-circuit debugger/programmer . the st ice is the fourth generation of full featured emulators from stmicroelectronics. it of fers new advanced debugging capabilities including profiling and coverage to help detect and eliminate bottlenecks in application execution and dead code when fine tuning an application. in addition, st ice of fers in-circuit debugging and programming of stm8 microcontrollers via the stm8 single wire interface module (swim), which allows non-intrusive debugging of an application while it runs on the target microcontroller . for improved cost ef fectiveness, st ice is based on a modular design that allows you to order exactly what you need to meet your development requirements and to adapt your emulation system to support existing and future st microcontrollers. st ice key features ? occurrence and time profiling and code coverage (new features) ? advanced breakpoints with up to 4 levels of conditions ? data breakpoints ? program and data trace recording up to 128 kb records ? read/write on the fly of memory during emulation ? in-circuit debugging/programming via swim protocol ? 8-bit probe analyzer ? 1 input and 2 output triggers ? power supply follower managing application voltages between 1.62 to 5.5 v ? modularity that allows you to specify the components you need to meet your development requirements and adapt to future requirements ? supported by free software tools that include integrated development environment (ide), programming software interface and assembler for stm8. software tools 13.2 stm8 development tools are supported by a complete, free software package from stmicroelectronics that includes st v isual develop (stvd) ide and the st v isual programmer (stvp) software interface. stvd provides seamless integration of the cosmic and raisonance c compilers for stm8, which are available in a free version that outputs up to 16 kbytes of code. docid022186 rev 3 100 / 103 stm8s005k6 stm8s005c6 stm8 development tools
stm8 toolset 13.2.1 stm8 toolset with stvd integrated development environment and stvp programming software is available for free download at www .st.com/mcu. this package includes: st v isual develop C full-featured integrated development environment from st , featuring ? seamless integration of c and asm toolsets ? full-featured debugger ? project management ? syntax highlighting editor ? integrated programming interface ? support of advanced emulation features for st ice such as code profiling and coverage st v isual programmer (stvp) C easy-to-use, unlimited graphical interface allowing read, write and verify of your stm8 microcontroller s flash program memory , data eeprom and option bytes. stvp also of fers project mode for saving programming configurations and automating programming sequences. c and assembly toolchains 13.2.2 control of c and assembly toolchains is seamlessly integrated into the stvd integrated development environment, making it possible to configure and control the building of your application directly from an easy-to-use graphical interface. a vailable toolchains include: ? cosmic c compiler for stm8 C a vailable in a free version that outputs up to 16 kbytes of code. for more information, see www .cosmic-software.com. ? raisonance c compiler for stm8 C a vailable in a free version that outputs up to 16 kbytes of code. for more information, see www .raisonance.com. ? stm8 assembler linker C free assembly toolchain included in the stvd toolset, which allows you to assemble and link your application source code. programming tools 13.3 during the development cycle, st ice provides in-circuit programming of the stm8 flash microcontroller on your application board via the swim protocol. additional tools are to include a low-cost in-circuit programmer as well as st socket boards, which provide dedicated programming platforms with sockets for programming your stm8. for production environments, programmers will include a complete range of gang and automated programming solutions from third-party tool developers already supplying programmers for the stm8 family . 101 / 103 docid022186 rev 3 stm8 development tools stm8s005k6 stm8s005c6
revision history 14 t able 53: document revision history changes revision date initial release. 1 14-oct-201 1 updated t ret in t able 35: flash program memory/data eeprom memory . 2 09-jan-2012 updated r pu in t able 40: nrst pin characteristics and t able 36: i/o static characteristics . updated notes related to v cap in operating conditions . updated temperature condition for factory calibrated acc hsi in t able 32: hsi oscillator characteristics . changed sck input to sck output in figure 40: spi timing diagram - master mode(1) . 3 13-jun-2012 docid022186 rev 3 102 / 103 stm8s005k6 stm8s005c6 revision history
please read carefully information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (st) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at anytime, without notice. all st products are sold pursuant to st s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st assumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. if any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. unless other wise set forth in sts terms and conditions of sale st disclaims any express or implied w arranty with respect t o the use and/or sale of st products including without limit a tion implied w arranties of merchant ability , fitness for a p articular purpose (and their equiv alents under the la ws of any jurisdiction), or infringement of any p a tent , copyright or other intellectual property right . unless expressl y approved in writing by two authorized st represent a tives, st products are not recommended, authorized or w arranted for use in milit ar y , air craft , sp ace, life sa ving, or life sust aining applica tions, nor in products or systems where f ailure or malfunction ma y resul t in personal injur y , dea th, or severe property or environment al damage. st products which are not specified as "aut omotive grade" ma y onl y be used in aut omotive applica tions a t users own risk. resale of st products with provisions dif ferent from the statements and/or technical features set forth in this document shall immediately voidany warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoever , any liability of st . st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 201 1 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www .st.com 103 / 103 docid022186 rev 3 stm8s005k6 stm8s005c6

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